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authorAndrew Cagney <cagney@gnu.org>2002-06-01 18:15:42 +0000
committerAndrew Cagney <cagney@gnu.org>2002-06-01 18:15:42 +0000
commit84c32f59067b5ea18f2a11ee2e0598503e5e1c7e (patch)
treef60669870f6a58ff1c9ab49fa5f73964dcb9bc15 /include
parent28af03faed3f79e2d8e284f1fc83adb6a0c4f193 (diff)
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Fill-out d10v enum so that there are no ``=''.
Diffstat (limited to 'include')
-rw-r--r--include/gdb/ChangeLog5
-rw-r--r--include/gdb/sim-d10v.h76
2 files changed, 61 insertions, 20 deletions
diff --git a/include/gdb/ChangeLog b/include/gdb/ChangeLog
index e0992c9..44e3582 100644
--- a/include/gdb/ChangeLog
+++ b/include/gdb/ChangeLog
@@ -1,3 +1,8 @@
+2002-06-01 Andrew Cagney <ac131313@redhat.com>
+
+ * sim-d10v.h (sim_d10v_regs): Expand to include all registers.
+ Update copyright.
+
2002-05-23 Andrew Cagney <ac131313@redhat.com>
* sim-d10v.h: New file. Moved from include/sim-d10v.h.
diff --git a/include/gdb/sim-d10v.h b/include/gdb/sim-d10v.h
index 9d29e05..f153a41 100644
--- a/include/gdb/sim-d10v.h
+++ b/include/gdb/sim-d10v.h
@@ -1,5 +1,6 @@
/* This file defines the interface between the d10v simulator and gdb.
- Copyright 1999 Free Software Foundation, Inc.
+
+ Copyright 1999, 2002 Free Software Foundation, Inc.
This file is part of GDB.
@@ -75,26 +76,61 @@ extern unsigned long sim_d10v_translate_addr
/* The simulator makes use of the following register information. */
+enum sim_d10v_regs
+{
+ SIM_D10V_R0_REGNUM,
+ SIM_D10V_R1_REGNUM,
+ SIM_D10V_R2_REGNUM,
+ SIM_D10V_R3_REGNUM,
+ SIM_D10V_R4_REGNUM,
+ SIM_D10V_R5_REGNUM,
+ SIM_D10V_R6_REGNUM,
+ SIM_D10V_R7_REGNUM,
+ SIM_D10V_R8_REGNUM,
+ SIM_D10V_R9_REGNUM,
+ SIM_D10V_R10_REGNUM,
+ SIM_D10V_R11_REGNUM,
+ SIM_D10V_R12_REGNUM,
+ SIM_D10V_R13_REGNUM,
+ SIM_D10V_R14_REGNUM,
+ SIM_D10V_R15_REGNUM,
+ SIM_D10V_CR0_REGNUM,
+ SIM_D10V_CR1_REGNUM,
+ SIM_D10V_CR2_REGNUM,
+ SIM_D10V_CR3_REGNUM,
+ SIM_D10V_CR4_REGNUM,
+ SIM_D10V_CR5_REGNUM,
+ SIM_D10V_CR6_REGNUM,
+ SIM_D10V_CR7_REGNUM,
+ SIM_D10V_CR8_REGNUM,
+ SIM_D10V_CR9_REGNUM,
+ SIM_D10V_CR10_REGNUM,
+ SIM_D10V_CR11_REGNUM,
+ SIM_D10V_CR12_REGNUM,
+ SIM_D10V_CR13_REGNUM,
+ SIM_D10V_CR14_REGNUM,
+ SIM_D10V_CR15_REGNUM,
+ SIM_D10V_A0_REGNUM,
+ SIM_D10V_A1_REGNUM,
+ SIM_D10V_SPI_REGNUM,
+ SIM_D10V_SPU_REGNUM,
+ SIM_D10V_IMAP0_REGNUM,
+ SIM_D10V_IMAP1_REGNUM,
+ SIM_D10V_DMAP0_REGNUM,
+ SIM_D10V_DMAP1_REGNUM,
+ SIM_D10V_DMAP2_REGNUM,
+ SIM_D10V_DMAP3_REGNUM,
+ SIM_D10V_TS2_DMAP_REGNUM
+};
+
enum
- {
- SIM_D10V_R0_REGNUM = 0,
- SIM_D10V_CR0_REGNUM = 16,
- SIM_D10V_A0_REGNUM = 32,
- SIM_D10V_SPI_REGNUM = 34,
- SIM_D10V_SPU_REGNUM = 35,
- SIM_D10V_IMAP0_REGNUM = 36,
- SIM_D10V_DMAP0_REGNUM = 38,
- SIM_D10V_TS2_DMAP_REGNUM = 40
- };
-
-enum
- {
- SIM_D10V_NR_R_REGS = 16,
- SIM_D10V_NR_A_REGS = 2,
- SIM_D10V_NR_IMAP_REGS = 2,
- SIM_D10V_NR_DMAP_REGS = 4,
- SIM_D10V_NR_CR_REGS = 16
- };
+{
+ SIM_D10V_NR_R_REGS = 16,
+ SIM_D10V_NR_A_REGS = 2,
+ SIM_D10V_NR_IMAP_REGS = 2,
+ SIM_D10V_NR_DMAP_REGS = 4,
+ SIM_D10V_NR_CR_REGS = 16
+};
#ifdef __cplusplus
}