Add MIPS32 as a seperate MIPS architecture

5 files changed, 286 insertions, 259 deletions

diff --git a/config.sub b/config.sub
index af79d70..f8d46e4 100755
--- a/config.sub
+++ b/config.sub
@@ -211,10 +211,11 @@ esac
 case $basic_machine in
 	# Recognize the basic CPU types without company name.
 	# Some are omitted here because they have special meanings below.
-	tahoe | i860 | ia64 | m32r | m68k | m68000 | m88k | ns32k | arc | arm \
-		| arme[lb] | armv[2345] | armv[345][lb] | pyramid | mn10200 | mn10300 | tron | a29k \
+	tahoe | i860 | ia64 | m32r | m68k | m68000 | m88k | ns32k | arc \
+	        | arm | arme[lb] | arm[bl]e | armv[2345] | armv[345][lb] | strongarm | xscale \
+		| pyramid | mn10200 | mn10300 | tron | a29k \
 		| 580 | i960 | h8300 \
-		| x86 | ppcbe | mipsbe | mipsle | shbe | shle | armbe | armle \
+		| x86 | ppcbe | mipsbe | mipsle | shbe | shle \
 		| hppa | hppa1.0 | hppa1.1 | hppa2.0 | hppa2.0w | hppa2.0n \
 		| hppa64 \
 		| alpha | alphaev[4-8] | alphaev56 | alphapca5[67] \
@@ -251,11 +252,12 @@ case $basic_machine in
 	# Recognize the basic CPU types with company name.
 	# FIXME: clean up the formatting here.
 	vax-* | tahoe-* | i[234567]86-* | i860-* | ia64-* | m32r-* | m68k-* | m68000-* \
-	      | m88k-* | sparc-* | ns32k-* | fx80-* | arc-* | arm-* | c[123]* \
+	      | m88k-* | sparc-* | ns32k-* | fx80-* | arc-* | c[123]* \
+	      | arm-*  | armbe-* | armle-* | armv*-* | strongarm-* | xscale-* \
 	      | mips-* | pyramid-* | tron-* | a29k-* | romp-* | rs6000-* \
 	      | power-* | none-* | 580-* | cray2-* | h8300-* | h8500-* | i960-* \
 	      | xmp-* | ymp-* \
-	      | x86-* | ppcbe-* | mipsbe-* | mipsle-* | shbe-* | shle-* | armbe-* | armle-* \
+	      | x86-* | ppcbe-* | mipsbe-* | mipsle-* | shbe-* | shle-* \
 	      | hppa-* | hppa1.0-* | hppa1.1-* | hppa2.0-* | hppa2.0w-* \
 	      | hppa2.0n-* | hppa64-* \
 	      | alpha-* | alphaev[4-8]-* | alphaev56-* | alphapca5[67]-* \
@@ -267,7 +269,7 @@ case $basic_machine in
 	      | mips64el-* | mips64orion-* | mips64orionel-* \
 	      | mips64vr4100-* | mips64vr4100el-* | mips64vr4300-* | mips64vr4300el-* \
 	      | mipstx39-* | mipstx39el-* | mcore-* \
-	      | f301-* | armv*-* | s390-* | sv1-* | t3e-* \
+	      | f301-* | s390-* | sv1-* | t3e-* \
 	      | m88110-* | m680[01234]0-* | m683?2-* | m68360-* | z8k-* | d10v-* \
 	      | thumb-* | v850-* | d30v-* | tic30-* | c30-* | fr30-* \
 	      | bs2000-* | tic54x-* | c54x-* | x86_64-*)
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index aa2d4e0..a1ef885 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,9 @@
+2000-10-16  Chris Demetriou  <cgd@sibyte.com>
+
+        * mips.h (E_MIPS_ARCH_32): New constant.
+        (E_MIPS_MACH_MIPS32, E_MIPS_MACH_MIPS32_4K): Replace the
+        former with the latter. 
+
 2000-11-30  Jan Hubicka  <jh@suse.cz>
 	
         * common.h (EM_X86_64): New macro.
diff --git a/include/elf/mips.h b/include/elf/mips.h
index 18185e7..41f52cd 100644
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -121,6 +121,9 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
 /* -mips4 code.  */
 #define E_MIPS_ARCH_4		0x30000000
 
+/* -mips32 code.  */
+#define E_MIPS_ARCH_32                0x50000000
+
 /* The ABI of the file.  Also see EF_MIPS_ABI2 above. */
 #define EF_MIPS_ABI		0x0000F000
 
@@ -153,9 +156,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
 #define E_MIPS_MACH_4100	0x00830000
 #define E_MIPS_MACH_4650	0x00850000
 #define E_MIPS_MACH_4111	0x00880000
-/* -mips32 code.
-   It is easier to treat MIPS32 as a machine rather than an architecture.  */
-#define E_MIPS_MACH_MIPS32	0x00890000
+#define E_MIPS_MACH_MIPS32_4K	0x00890000
 
 /* Processor specific section indices.  These sections do not actually
    exist.  Symbols with a st_shndx field corresponding to one of these
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 902544a..ceb0317 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -8,6 +8,23 @@
         (MIPS operand specifier comments): Remove 'm', add 'U' and
         'J', and update the meaning of 'B' so that it's more general.
 
+        * mips.h (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4,
+        INSN_ISA5): Renumber, redefine to mean the ISA at which the
+        instruction was added.
+        (INSN_ISA32): New constant.
+        (INSN_4650, INSN_4010, INSN_4100, INSN_3900, INSN_GP32):
+        Renumber to avoid new and/or renumbered INSN_* constants.
+        (INSN_MIPS32): Delete.
+        (ISA_UNKNOWN): New constant to indicate unknown ISA.
+        (ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS5,
+        ISA_MIPS32): New constants, defined to be the mask of INSN_*
+        constants available at that ISA level. 
+        (CPU_UNKNOWN): New constant to indicate unknown CPU.
+        (CPU_4K, CPU_MIPS32_4K): Rename the former to the latter,
+        define it with a unique value.
+        (OPCODE_IS_MEMBER): Update for new ISA membership-related
+        constant meanings.
+
 2000-10-20  Jakub Jelinek  <jakub@redhat.com>
 
 	* sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 61931f6..7eaba30 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -302,41 +302,43 @@ struct mips_opcode
    disassembler, and requires special treatment by the assembler.  */
 #define INSN_MACRO                  0xffffffff
 
-
-
-
-
-/* MIPS ISA field--CPU level at which insn is supported.  */
-#define INSN_ISA		    0x0000000F
-/* An instruction which is not part of any basic MIPS ISA.
-   (ie it is a chip specific instruction)  */
-#define INSN_NO_ISA		    0x00000000
-/* MIPS ISA 1 instruction.  */
-#define INSN_ISA1		    0x00000001
-/* MIPS ISA 2 instruction (R6000 or R4000).  */
-#define INSN_ISA2		    0x00000002
-/* MIPS ISA 3 instruction (R4000).  */
-#define INSN_ISA3		    0x00000003
-/* MIPS ISA 4 instruction (R8000).  */
-#define INSN_ISA4		    0x00000004
-#define INSN_ISA5		    0x00000005
+/* Masks used to mark instructions to indicate which MIPS ISA level
+   they were introduced in.  ISAs, as defined below, are logical
+   ORs of these bits, indicatingthat they support the instructions
+   defined at the given level.  */
+
+#define INSN_ISA1                 0x00000010
+#define INSN_ISA2                 0x00000020
+#define INSN_ISA3                 0x00000040
+#define INSN_ISA4                 0x00000080
+#define INSN_ISA5                 0x00000100
+#define INSN_ISA32                0x00000200
 
 /* Chip specific instructions.  These are bitmasks.  */
+
 /* MIPS R4650 instruction.  */
-#define INSN_4650		    0x00000010
+#define INSN_4650                 0x00010000
 /* LSI R4010 instruction.  */
-#define INSN_4010		    0x00000020
-/* NEC VR4100 instruction. */
-#define INSN_4100                   0x00000040
+#define INSN_4010                 0x00020000
+/* NEC VR4100 instruction.  */
+#define INSN_4100                   0x00040000
 /* Toshiba R3900 instruction.  */
-#define INSN_3900                   0x00000080
-/* MIPS32 instruction (4Kc, 4Km, 4Kp).  */
-#define INSN_MIPS32                 0x00000100
-/* 32-bit code running on a ISA3+ CPU. */
-#define INSN_GP32                   0x00001000
+#define INSN_3900                   0x00080000
+/* 32-bit code running on a ISA3+ CPU.  */
+#define INSN_GP32                   0x00100000
+
+/* MIPS ISA defines, use instead of hardcoding ISA level.  */
+
+#define       ISA_UNKNOWN     0               /* Gas internal use.  */
+#define       ISA_MIPS1       (INSN_ISA1)
+#define       ISA_MIPS2       (ISA_MIPS1 | INSN_ISA2)
+#define       ISA_MIPS3       (ISA_MIPS2 | INSN_ISA3)
+#define       ISA_MIPS4       (ISA_MIPS3 | INSN_ISA4)
+#define       ISA_MIPS32      (ISA_MIPS2 | INSN_ISA32)
 
 /* CPU defines, use instead of hardcoding processor number. Keep this
    in sync with bfd/archures.c in order for machine selection to work.  */
+#define CPU_UNKNOWN	0               /* Gas internal use.  */
 #define CPU_R2000	2000
 #define CPU_R3000	3000
 #define CPU_R3900	3900
@@ -354,7 +356,7 @@ struct mips_opcode
 #define CPU_R10000	10000
 #define CPU_MIPS16	16
 #define CPU_MIPS32	32
-#define CPU_4K		CPU_MIPS32
+#define CPU_MIPS32_4K	3204113         /* 32, 04, octal 'K' */
 
 /* Test for membership in an ISA including chip specific ISAs.
    INSN is pointer to an element of the opcode table; ISA is the
@@ -365,236 +367,235 @@ struct mips_opcode
    in the MIPS gas docs. */
 
 #define OPCODE_IS_MEMBER(insn, isa, cpu, gp32)				\
-    ((((insn)->membership & INSN_ISA) != 0				\
-      && ((insn)->membership & INSN_ISA) <= (unsigned) isa		\
+    ((((insn)->membership & isa) != 0                           	\
       && ((insn)->membership & INSN_GP32 ? gp32 : 1))			\
      || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)	\
      || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)	\
      || ((cpu == CPU_VR4100 || cpu == CPU_R4111)			\
 	 && ((insn)->membership & INSN_4100) != 0)			\
-     || (cpu == CPU_MIPS32 && ((insn)->membership & INSN_MIPS32) != 0)	\
      || (cpu == CPU_R3900  && ((insn)->membership & INSN_3900) != 0))
 
 /* This is a list of macro expanded instructions.
- *
- * _I appended means immediate
- * _A appended means address
- * _AB appended means address with base register
- * _D appended means 64 bit floating point constant
- * _S appended means 32 bit floating point constant
- */
-enum {
-    M_ABS,
-    M_ADD_I,
-    M_ADDU_I,
-    M_AND_I,
-    M_BEQ,
-    M_BEQ_I,
-    M_BEQL_I,
-    M_BGE,
-    M_BGEL,
-    M_BGE_I,
-    M_BGEL_I,
-    M_BGEU,
-    M_BGEUL,
-    M_BGEU_I,
-    M_BGEUL_I,
-    M_BGT,
-    M_BGTL,
-    M_BGT_I,
-    M_BGTL_I,
-    M_BGTU,
-    M_BGTUL,
-    M_BGTU_I,
-    M_BGTUL_I,
-    M_BLE,
-    M_BLEL,
-    M_BLE_I,
-    M_BLEL_I,
-    M_BLEU,
-    M_BLEUL,
-    M_BLEU_I,
-    M_BLEUL_I,
-    M_BLT,
-    M_BLTL,
-    M_BLT_I,
-    M_BLTL_I,
-    M_BLTU,
-    M_BLTUL,
-    M_BLTU_I,
-    M_BLTUL_I,
-    M_BNE,
-    M_BNE_I,
-    M_BNEL_I,
-    M_DABS,
-    M_DADD_I,
-    M_DADDU_I,
-    M_DDIV_3,
-    M_DDIV_3I,
-    M_DDIVU_3,
-    M_DDIVU_3I,
-    M_DIV_3,
-    M_DIV_3I,
-    M_DIVU_3,
-    M_DIVU_3I,
-    M_DLA_AB,
-    M_DLI,
-    M_DMUL,
-    M_DMUL_I, 
-    M_DMULO,
-    M_DMULO_I, 
-    M_DMULOU,
-    M_DMULOU_I, 
-    M_DREM_3,
-    M_DREM_3I,
-    M_DREMU_3,
-    M_DREMU_3I,
-    M_DSUB_I,
-    M_DSUBU_I,
-    M_DSUBU_I_2,
-    M_J_A,
-    M_JAL_1,
-    M_JAL_2,
-    M_JAL_A,
-    M_L_DOB,
-    M_L_DAB,
-    M_LA_AB,
-    M_LB_A,
-    M_LB_AB,
-    M_LBU_A,
-    M_LBU_AB,
-    M_LD_A,
-    M_LD_OB,
-    M_LD_AB,
-    M_LDC1_AB,
-    M_LDC2_AB,
-    M_LDC3_AB,
-    M_LDL_AB,
-    M_LDR_AB,
-    M_LH_A,
-    M_LH_AB,
-    M_LHU_A,
-    M_LHU_AB,
-    M_LI,
-    M_LI_D,
-    M_LI_DD,
-    M_LI_S,
-    M_LI_SS,
-    M_LL_AB,
-    M_LLD_AB,
-    M_LS_A,
-    M_LW_A,
-    M_LW_AB,
-    M_LWC0_A,
-    M_LWC0_AB,
-    M_LWC1_A,
-    M_LWC1_AB,
-    M_LWC2_A,
-    M_LWC2_AB,
-    M_LWC3_A,
-    M_LWC3_AB,
-    M_LWL_A,
-    M_LWL_AB,
-    M_LWR_A,
-    M_LWR_AB,
-    M_LWU_AB,
-    M_MUL,
-    M_MUL_I, 
-    M_MULO,
-    M_MULO_I, 
-    M_MULOU,
-    M_MULOU_I, 
-    M_NOR_I,
-    M_OR_I,
-    M_REM_3,
-    M_REM_3I,
-    M_REMU_3,
-    M_REMU_3I,
-    M_ROL,
-    M_ROL_I,
-    M_ROR,
-    M_ROR_I,
-    M_S_DA,
-    M_S_DOB,
-    M_S_DAB,
-    M_S_S,
-    M_SC_AB,
-    M_SCD_AB,
-    M_SD_A,
-    M_SD_OB,
-    M_SD_AB,
-    M_SDC1_AB,
-    M_SDC2_AB,
-    M_SDC3_AB,
-    M_SDL_AB,
-    M_SDR_AB,
-    M_SEQ,
-    M_SEQ_I,
-    M_SGE,
-    M_SGE_I,
-    M_SGEU,
-    M_SGEU_I,
-    M_SGT,
-    M_SGT_I,
-    M_SGTU,
-    M_SGTU_I,
-    M_SLE,
-    M_SLE_I,
-    M_SLEU,
-    M_SLEU_I,
-    M_SLT_I,
-    M_SLTU_I,
-    M_SNE,
-    M_SNE_I,
-    M_SB_A,
-    M_SB_AB,
-    M_SH_A,
-    M_SH_AB,
-    M_SW_A,
-    M_SW_AB,
-    M_SWC0_A,
-    M_SWC0_AB,
-    M_SWC1_A,
-    M_SWC1_AB,
-    M_SWC2_A,
-    M_SWC2_AB,
-    M_SWC3_A,
-    M_SWC3_AB,
-    M_SWL_A,
-    M_SWL_AB,
-    M_SWR_A,
-    M_SWR_AB,
-    M_SUB_I,
-    M_SUBU_I,
-    M_SUBU_I_2,
-    M_TEQ_I,
-    M_TGE_I,
-    M_TGEU_I,
-    M_TLT_I,
-    M_TLTU_I,
-    M_TNE_I,
-    M_TRUNCWD,
-    M_TRUNCWS,
-    M_ULD,
-    M_ULD_A,
-    M_ULH,
-    M_ULH_A,
-    M_ULHU,
-    M_ULHU_A,
-    M_ULW,
-    M_ULW_A,
-    M_USH,
-    M_USH_A,
-    M_USW,
-    M_USW_A,
-    M_USD,
-    M_USD_A,
-    M_XOR_I,
-    M_COP0,
-    M_COP1,
-    M_COP2,
-    M_COP3,
-    M_NUM_MACROS
+  
+   _I appended means immediate
+   _A appended means address
+   _AB appended means address with base register
+   _D appended means 64 bit floating point constant
+   _S appended means 32 bit floating point constant.  */
+
+enum
+{
+  M_ABS,
+  M_ADD_I,
+  M_ADDU_I,
+  M_AND_I,
+  M_BEQ,
+  M_BEQ_I,
+  M_BEQL_I,
+  M_BGE,
+  M_BGEL,
+  M_BGE_I,
+  M_BGEL_I,
+  M_BGEU,
+  M_BGEUL,
+  M_BGEU_I,
+  M_BGEUL_I,
+  M_BGT,
+  M_BGTL,
+  M_BGT_I,
+  M_BGTL_I,
+  M_BGTU,
+  M_BGTUL,
+  M_BGTU_I,
+  M_BGTUL_I,
+  M_BLE,
+  M_BLEL,
+  M_BLE_I,
+  M_BLEL_I,
+  M_BLEU,
+  M_BLEUL,
+  M_BLEU_I,
+  M_BLEUL_I,
+  M_BLT,
+  M_BLTL,
+  M_BLT_I,
+  M_BLTL_I,
+  M_BLTU,
+  M_BLTUL,
+  M_BLTU_I,
+  M_BLTUL_I,
+  M_BNE,
+  M_BNE_I,
+  M_BNEL_I,
+  M_DABS,
+  M_DADD_I,
+  M_DADDU_I,
+  M_DDIV_3,
+  M_DDIV_3I,
+  M_DDIVU_3,
+  M_DDIVU_3I,
+  M_DIV_3,
+  M_DIV_3I,
+  M_DIVU_3,
+  M_DIVU_3I,
+  M_DLA_AB,
+  M_DLI,
+  M_DMUL,
+  M_DMUL_I, 
+  M_DMULO,
+  M_DMULO_I, 
+  M_DMULOU,
+  M_DMULOU_I, 
+  M_DREM_3,
+  M_DREM_3I,
+  M_DREMU_3,
+  M_DREMU_3I,
+  M_DSUB_I,
+  M_DSUBU_I,
+  M_DSUBU_I_2,
+  M_J_A,
+  M_JAL_1,
+  M_JAL_2,
+  M_JAL_A,
+  M_L_DOB,
+  M_L_DAB,
+  M_LA_AB,
+  M_LB_A,
+  M_LB_AB,
+  M_LBU_A,
+  M_LBU_AB,
+  M_LD_A,
+  M_LD_OB,
+  M_LD_AB,
+  M_LDC1_AB,
+  M_LDC2_AB,
+  M_LDC3_AB,
+  M_LDL_AB,
+  M_LDR_AB,
+  M_LH_A,
+  M_LH_AB,
+  M_LHU_A,
+  M_LHU_AB,
+  M_LI,
+  M_LI_D,
+  M_LI_DD,
+  M_LI_S,
+  M_LI_SS,
+  M_LL_AB,
+  M_LLD_AB,
+  M_LS_A,
+  M_LW_A,
+  M_LW_AB,
+  M_LWC0_A,
+  M_LWC0_AB,
+  M_LWC1_A,
+  M_LWC1_AB,
+  M_LWC2_A,
+  M_LWC2_AB,
+  M_LWC3_A,
+  M_LWC3_AB,
+  M_LWL_A,
+  M_LWL_AB,
+  M_LWR_A,
+  M_LWR_AB,
+  M_LWU_AB,
+  M_MUL,
+  M_MUL_I, 
+  M_MULO,
+  M_MULO_I, 
+  M_MULOU,
+  M_MULOU_I, 
+  M_NOR_I,
+  M_OR_I,
+  M_REM_3,
+  M_REM_3I,
+  M_REMU_3,
+  M_REMU_3I,
+  M_ROL,
+  M_ROL_I,
+  M_ROR,
+  M_ROR_I,
+  M_S_DA,
+  M_S_DOB,
+  M_S_DAB,
+  M_S_S,
+  M_SC_AB,
+  M_SCD_AB,
+  M_SD_A,
+  M_SD_OB,
+  M_SD_AB,
+  M_SDC1_AB,
+  M_SDC2_AB,
+  M_SDC3_AB,
+  M_SDL_AB,
+  M_SDR_AB,
+  M_SEQ,
+  M_SEQ_I,
+  M_SGE,
+  M_SGE_I,
+  M_SGEU,
+  M_SGEU_I,
+  M_SGT,
+  M_SGT_I,
+  M_SGTU,
+  M_SGTU_I,
+  M_SLE,
+  M_SLE_I,
+  M_SLEU,
+  M_SLEU_I,
+  M_SLT_I,
+  M_SLTU_I,
+  M_SNE,
+  M_SNE_I,
+  M_SB_A,
+  M_SB_AB,
+  M_SH_A,
+  M_SH_AB,
+  M_SW_A,
+  M_SW_AB,
+  M_SWC0_A,
+  M_SWC0_AB,
+  M_SWC1_A,
+  M_SWC1_AB,
+  M_SWC2_A,
+  M_SWC2_AB,
+  M_SWC3_A,
+  M_SWC3_AB,
+  M_SWL_A,
+  M_SWL_AB,
+  M_SWR_A,
+  M_SWR_AB,
+  M_SUB_I,
+  M_SUBU_I,
+  M_SUBU_I_2,
+  M_TEQ_I,
+  M_TGE_I,
+  M_TGEU_I,
+  M_TLT_I,
+  M_TLTU_I,
+  M_TNE_I,
+  M_TRUNCWD,
+  M_TRUNCWS,
+  M_ULD,
+  M_ULD_A,
+  M_ULH,
+  M_ULH_A,
+  M_ULHU,
+  M_ULHU_A,
+  M_ULW,
+  M_ULW_A,
+  M_USH,
+  M_USH_A,
+  M_USW,
+  M_USW_A,
+  M_USD,
+  M_USD_A,
+  M_XOR_I,
+  M_COP0,
+  M_COP1,
+  M_COP2,
+  M_COP3,
+  M_NUM_MACROS
 };