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authorMaciej W. Rozycki <macro@codesourcery.com>2012-07-06 14:20:22 +0000
committerMaciej W. Rozycki <macro@codesourcery.com>2012-07-06 14:20:22 +0000
commite75fa972ac783e0b87bcdfd625fe4f199bafd8ee (patch)
tree9d4e97e496fc975be4564a335959679f83a32590
parent44fb3af98addbbcd300f7123d0c2c90845fe0bd2 (diff)
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* mips.h: Fix a typo in description.
-rw-r--r--include/opcode/ChangeLog4
-rw-r--r--include/opcode/mips.h2
2 files changed, 5 insertions, 1 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index a454ad0..4b8d300 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips.h: Fix a typo in description.
+
2012-06-07 Georg-Johann Lay <avr@gjlay.de>
* avr.h: (AVR_ISA_XCH): New define.
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index fb9094c..9232508 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -1646,7 +1646,7 @@ extern const int bfd_mips16_num_opcodes;
"y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3)
"z" must be zero register
"C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ)
- "B" 8-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
+ "B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
"K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS)
"+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes