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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; Verify whether the generated assembly for the following function includes the mtvsrbmi instruction.
; vector unsigned char v00FF()
; {
; vector unsigned char x = { 0xFF, 0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0 };
; return x;
; }
; RUN: llc < %s -ppc-asm-full-reg-names -mtriple=powerpc-ibm-aix -mcpu=pwr10 -verify-machineinstrs \
; RUN: | FileCheck %s --check-prefix=CHECK
define dso_local noundef range(i8 -1, 1) <16 x i8> @_Z5v00FFv() {
; CHECK: L..CPI0_0:
; CHECK-NEXT: .byte 255 # 0xff
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-LABEL: _Z5v00FFv:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz r3, L..C0(r2) # %const.0
; CHECK-NEXT: lxv vs34, 0(r3)
; CHECK-NEXT: blr
entry:
ret <16 x i8> <i8 -1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
}
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