; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 ; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu -slp-threshold=-99999 -mattr=+sse4.1 < %s | FileCheck %s define void @test(i32 %arg) { ; CHECK-LABEL: define void @test( ; CHECK-SAME: i32 [[ARG:%.*]]) #[[ATTR0:[0-9]+]] { ; CHECK-NEXT: [[BB:.*:]] ; CHECK-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(3) null, align 4 ; CHECK-NEXT: [[LOAD1:%.*]] = load i32, ptr addrspace(3) null, align 4 ; CHECK-NEXT: [[LOAD2:%.*]] = load i32, ptr addrspace(3) null, align 4 ; CHECK-NEXT: [[LOAD3:%.*]] = load i32, ptr addrspace(3) null, align 4 ; CHECK-NEXT: br label %[[BB4:.*]] ; CHECK: [[BB4]]: ; CHECK-NEXT: switch i32 0, label %[[BB8:.*]] [ ; CHECK-NEXT: i32 0, label %[[BB7:.*]] ; CHECK-NEXT: i32 1, label %[[BB21:.*]] ; CHECK-NEXT: ] ; CHECK: [[BB5:.*:]] ; CHECK-NEXT: br label %[[BB21]] ; CHECK: [[BB6:.*]]: ; CHECK-NEXT: br label %[[BB12:.*]] ; CHECK: [[BB7]]: ; CHECK-NEXT: ret void ; CHECK: [[BB8]]: ; CHECK-NEXT: [[TMP0:%.*]] = phi <4 x i32> [ zeroinitializer, %[[BB4]] ] ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[LOAD]], i32 0 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[LOAD1]], i32 1 ; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[LOAD3]], i32 2 ; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[LOAD2]], i32 3 ; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <8 x i32> ; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i32> [[TMP4]], <4 x i32> poison, <8 x i32> ; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <8 x i32> [[TMP5]], <8 x i32> [[TMP6]], <8 x i32> ; CHECK-NEXT: br label %[[BB12]] ; CHECK: [[BB12]]: ; CHECK-NEXT: [[TMP8:%.*]] = phi <8 x i32> [ [[TMP7]], %[[BB8]] ], [ poison, %[[BB6]] ] ; CHECK-NEXT: ret void ; CHECK: [[BB21]]: ; CHECK-NEXT: ret void ; bb: %load = load i32, ptr addrspace(3) null, align 4 %load1 = load i32, ptr addrspace(3) null, align 4 %load2 = load i32, ptr addrspace(3) null, align 4 %load3 = load i32, ptr addrspace(3) null, align 4 br label %bb4 bb4: switch i32 0, label %bb8 [ i32 0, label %bb7 i32 1, label %bb21 ] bb5: %srem = srem i32 0, 0 br label %bb21 bb6: br label %bb12 bb7: ret void bb8: %phi = phi i32 [ 0, %bb4 ] %phi9 = phi i32 [ 0, %bb4 ] %phi10 = phi i32 [ 0, %bb4 ] %phi11 = phi i32 [ 0, %bb4 ] br label %bb12 bb12: %phi13 = phi i32 [ %load, %bb8 ], [ 0, %bb6 ] %phi14 = phi i32 [ %load1, %bb8 ], [ 0, %bb6 ] %phi15 = phi i32 [ %load2, %bb8 ], [ %arg, %bb6 ] %phi16 = phi i32 [ %load3, %bb8 ], [ 0, %bb6 ] %phi17 = phi i32 [ %phi, %bb8 ], [ %srem, %bb6 ] %phi18 = phi i32 [ %phi11, %bb8 ], [ 0, %bb6 ] %phi19 = phi i32 [ %phi9, %bb8 ], [ 0, %bb6 ] %phi20 = phi i32 [ %phi10, %bb8 ], [ 0, %bb6 ] ret void bb21: ret void }