; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=riscv64 -mcpu=sifive-x280 -verify-machineinstrs < %s | FileCheck %s

define void @foo(<vscale x 8 x half> %0) {
; CHECK-LABEL: foo:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vmv.v.i v10, 0
; CHECK-NEXT:    lui a0, 1
; CHECK-NEXT:    addi a0, a0, -1096
; CHECK-NEXT:    vmv.v.i v11, 0
; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT:    #APP
; CHECK-NEXT:    vfmadd.vv v11, v10, v10
; CHECK-NEXT:    #NO_APP
; CHECK-NEXT:    #APP
; CHECK-NEXT:    vfmadd.vv v11, v10, v10
; CHECK-NEXT:    #NO_APP
; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT:    vse16.v v8, (zero)
; CHECK-NEXT:    ret
entry:
  %2 = tail call i64 @llvm.riscv.vsetvli.i64(i64 3000, i64 0, i64 0)
  %3 = tail call <vscale x 2 x float> asm sideeffect "vfmadd.vv $0, $1, $2", "=^vr,^vr,^vr,0"(<vscale x 2 x float> zeroinitializer, <vscale x 2 x float> zeroinitializer, <vscale x 2 x float> zeroinitializer)
  %4 = tail call <vscale x 2 x float> asm sideeffect "vfmadd.vv $0, $1, $2", "=^vr,^vr,^vr,0"(<vscale x 2 x float> zeroinitializer, <vscale x 2 x float> zeroinitializer, <vscale x 2 x float> %3)
  tail call void @llvm.riscv.vse.nxv8f16.i64(<vscale x 8 x half> %0, ptr null, i64 %2)
  ret void
}