; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \
; RUN:     -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
; RUN:     --check-prefixes=CHECK,ZVFH,RV32ZVFH
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \
; RUN:     -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
; RUN:     --check-prefixes=CHECK,ZVFH,RV64ZVFH
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \
; RUN:     -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
; RUN:     --check-prefixes=CHECK,ZVFHMIN,RV32ZVFHMIN
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \
; RUN:     -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
; RUN:     --check-prefixes=CHECK,ZVFHMIN,RV64ZVFHMIN

define <vscale x 1 x bfloat> @rint_nxv1bf16(<vscale x 1 x bfloat> %x) {
; CHECK-LABEL: rint_nxv1bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT:    vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT:    lui a0, 307200
; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT:    vfabs.v v8, v9
; CHECK-NEXT:    fmv.w.x fa5, a0
; CHECK-NEXT:    vmflt.vf v0, v8, fa5
; CHECK-NEXT:    vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT:    vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT:    vfsgnj.vv v9, v8, v9, v0.t
; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v9
; CHECK-NEXT:    ret
  %a = call <vscale x 1 x bfloat> @llvm.rint.nxv1bf16(<vscale x 1 x bfloat> %x)
  ret <vscale x 1 x bfloat> %a
}

define <vscale x 2 x bfloat> @rint_nxv2bf16(<vscale x 2 x bfloat> %x) {
; CHECK-LABEL: rint_nxv2bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT:    vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT:    lui a0, 307200
; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT:    vfabs.v v8, v9
; CHECK-NEXT:    fmv.w.x fa5, a0
; CHECK-NEXT:    vmflt.vf v0, v8, fa5
; CHECK-NEXT:    vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT:    vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT:    vfsgnj.vv v9, v8, v9, v0.t
; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v9
; CHECK-NEXT:    ret
  %a = call <vscale x 2 x bfloat> @llvm.rint.nxv2bf16(<vscale x 2 x bfloat> %x)
  ret <vscale x 2 x bfloat> %a
}

define <vscale x 4 x bfloat> @rint_nxv4bf16(<vscale x 4 x bfloat> %x) {
; CHECK-LABEL: rint_nxv4bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT:    vfwcvtbf16.f.f.v v10, v8
; CHECK-NEXT:    lui a0, 307200
; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT:    vfabs.v v8, v10
; CHECK-NEXT:    fmv.w.x fa5, a0
; CHECK-NEXT:    vmflt.vf v0, v8, fa5
; CHECK-NEXT:    vfcvt.x.f.v v8, v10, v0.t
; CHECK-NEXT:    vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
; CHECK-NEXT:    vfsgnj.vv v10, v8, v10, v0.t
; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v10
; CHECK-NEXT:    ret
  %a = call <vscale x 4 x bfloat> @llvm.rint.nxv4bf16(<vscale x 4 x bfloat> %x)
  ret <vscale x 4 x bfloat> %a
}

define <vscale x 8 x bfloat> @rint_nxv8bf16(<vscale x 8 x bfloat> %x) {
; CHECK-LABEL: rint_nxv8bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT:    vfwcvtbf16.f.f.v v12, v8
; CHECK-NEXT:    lui a0, 307200
; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT:    vfabs.v v8, v12
; CHECK-NEXT:    fmv.w.x fa5, a0
; CHECK-NEXT:    vmflt.vf v0, v8, fa5
; CHECK-NEXT:    vfcvt.x.f.v v8, v12, v0.t
; CHECK-NEXT:    vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
; CHECK-NEXT:    vfsgnj.vv v12, v8, v12, v0.t
; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v12
; CHECK-NEXT:    ret
  %a = call <vscale x 8 x bfloat> @llvm.rint.nxv8bf16(<vscale x 8 x bfloat> %x)
  ret <vscale x 8 x bfloat> %a
}

define <vscale x 16 x bfloat> @rint_nxv16bf16(<vscale x 16 x bfloat> %x) {
; CHECK-LABEL: rint_nxv16bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT:    vfwcvtbf16.f.f.v v16, v8
; CHECK-NEXT:    lui a0, 307200
; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT:    vfabs.v v8, v16
; CHECK-NEXT:    fmv.w.x fa5, a0
; CHECK-NEXT:    vmflt.vf v0, v8, fa5
; CHECK-NEXT:    vfcvt.x.f.v v8, v16, v0.t
; CHECK-NEXT:    vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
; CHECK-NEXT:    vfsgnj.vv v16, v8, v16, v0.t
; CHECK-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v16
; CHECK-NEXT:    ret
  %a = call <vscale x 16 x bfloat> @llvm.rint.nxv16bf16(<vscale x 16 x bfloat> %x)
  ret <vscale x 16 x bfloat> %a
}

define <vscale x 32 x bfloat> @rint_nxv32bf16(<vscale x 32 x bfloat> %x) {
; CHECK-LABEL: rint_nxv32bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT:    vfwcvtbf16.f.f.v v16, v8
; CHECK-NEXT:    lui a0, 307200
; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT:    vfabs.v v24, v16
; CHECK-NEXT:    fmv.w.x fa5, a0
; CHECK-NEXT:    vmflt.vf v0, v24, fa5
; CHECK-NEXT:    vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT:    vfcvt.f.x.v v24, v24, v0.t
; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
; CHECK-NEXT:    vfsgnj.vv v16, v24, v16, v0.t
; CHECK-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT:    vfwcvtbf16.f.f.v v24, v12
; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT:    vfabs.v v8, v24
; CHECK-NEXT:    vmflt.vf v0, v8, fa5
; CHECK-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v16
; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT:    vfcvt.x.f.v v16, v24, v0.t
; CHECK-NEXT:    vfcvt.f.x.v v16, v16, v0.t
; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
; CHECK-NEXT:    vfsgnj.vv v24, v16, v24, v0.t
; CHECK-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT:    vfncvtbf16.f.f.w v12, v24
; CHECK-NEXT:    ret
  %a = call <vscale x 32 x bfloat> @llvm.rint.nxv32bf16(<vscale x 32 x bfloat> %x)
  ret <vscale x 32 x bfloat> %a
}

define <vscale x 1 x half> @rint_nxv1f16(<vscale x 1 x half> %x) {
; ZVFH-LABEL: rint_nxv1f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
; ZVFH-NEXT:    vfabs.v v9, v8
; ZVFH-NEXT:    li a0, 25
; ZVFH-NEXT:    slli a0, a0, 10
; ZVFH-NEXT:    fmv.h.x fa5, a0
; ZVFH-NEXT:    vmflt.vf v0, v9, fa5
; ZVFH-NEXT:    vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT:    vfcvt.f.x.v v9, v9, v0.t
; ZVFH-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
; ZVFH-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: rint_nxv1f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT:    lui a0, 307200
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT:    vfabs.v v8, v9
; ZVFHMIN-NEXT:    fmv.w.x fa5, a0
; ZVFHMIN-NEXT:    vmflt.vf v0, v8, fa5
; ZVFHMIN-NEXT:    vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT:    vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT:    vfsgnj.vv v9, v8, v9, v0.t
; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT:    ret
  %a = call <vscale x 1 x half> @llvm.rint.nxv1f16(<vscale x 1 x half> %x)
  ret <vscale x 1 x half> %a
}
declare <vscale x 1 x half> @llvm.rint.nxv1f16(<vscale x 1 x half>)

define <vscale x 2 x half> @rint_nxv2f16(<vscale x 2 x half> %x) {
; ZVFH-LABEL: rint_nxv2f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
; ZVFH-NEXT:    vfabs.v v9, v8
; ZVFH-NEXT:    li a0, 25
; ZVFH-NEXT:    slli a0, a0, 10
; ZVFH-NEXT:    fmv.h.x fa5, a0
; ZVFH-NEXT:    vmflt.vf v0, v9, fa5
; ZVFH-NEXT:    vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT:    vfcvt.f.x.v v9, v9, v0.t
; ZVFH-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
; ZVFH-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: rint_nxv2f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT:    lui a0, 307200
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT:    vfabs.v v8, v9
; ZVFHMIN-NEXT:    fmv.w.x fa5, a0
; ZVFHMIN-NEXT:    vmflt.vf v0, v8, fa5
; ZVFHMIN-NEXT:    vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT:    vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT:    vfsgnj.vv v9, v8, v9, v0.t
; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT:    ret
  %a = call <vscale x 2 x half> @llvm.rint.nxv2f16(<vscale x 2 x half> %x)
  ret <vscale x 2 x half> %a
}
declare <vscale x 2 x half> @llvm.rint.nxv2f16(<vscale x 2 x half>)

define <vscale x 4 x half> @rint_nxv4f16(<vscale x 4 x half> %x) {
; ZVFH-LABEL: rint_nxv4f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; ZVFH-NEXT:    vfabs.v v9, v8
; ZVFH-NEXT:    li a0, 25
; ZVFH-NEXT:    slli a0, a0, 10
; ZVFH-NEXT:    fmv.h.x fa5, a0
; ZVFH-NEXT:    vmflt.vf v0, v9, fa5
; ZVFH-NEXT:    vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT:    vfcvt.f.x.v v9, v9, v0.t
; ZVFH-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
; ZVFH-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: rint_nxv4f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT:    lui a0, 307200
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT:    vfabs.v v8, v10
; ZVFHMIN-NEXT:    fmv.w.x fa5, a0
; ZVFHMIN-NEXT:    vmflt.vf v0, v8, fa5
; ZVFHMIN-NEXT:    vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT:    vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
; ZVFHMIN-NEXT:    vfsgnj.vv v10, v8, v10, v0.t
; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v10
; ZVFHMIN-NEXT:    ret
  %a = call <vscale x 4 x half> @llvm.rint.nxv4f16(<vscale x 4 x half> %x)
  ret <vscale x 4 x half> %a
}
declare <vscale x 4 x half> @llvm.rint.nxv4f16(<vscale x 4 x half>)

define <vscale x 8 x half> @rint_nxv8f16(<vscale x 8 x half> %x) {
; ZVFH-LABEL: rint_nxv8f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
; ZVFH-NEXT:    vfabs.v v10, v8
; ZVFH-NEXT:    li a0, 25
; ZVFH-NEXT:    slli a0, a0, 10
; ZVFH-NEXT:    fmv.h.x fa5, a0
; ZVFH-NEXT:    vmflt.vf v0, v10, fa5
; ZVFH-NEXT:    vfcvt.x.f.v v10, v8, v0.t
; ZVFH-NEXT:    vfcvt.f.x.v v10, v10, v0.t
; ZVFH-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
; ZVFH-NEXT:    vfsgnj.vv v8, v10, v8, v0.t
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: rint_nxv8f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT:    lui a0, 307200
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT:    vfabs.v v8, v12
; ZVFHMIN-NEXT:    fmv.w.x fa5, a0
; ZVFHMIN-NEXT:    vmflt.vf v0, v8, fa5
; ZVFHMIN-NEXT:    vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT:    vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
; ZVFHMIN-NEXT:    vfsgnj.vv v12, v8, v12, v0.t
; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT:    ret
  %a = call <vscale x 8 x half> @llvm.rint.nxv8f16(<vscale x 8 x half> %x)
  ret <vscale x 8 x half> %a
}
declare <vscale x 8 x half> @llvm.rint.nxv8f16(<vscale x 8 x half>)

define <vscale x 16 x half> @rint_nxv16f16(<vscale x 16 x half> %x) {
; ZVFH-LABEL: rint_nxv16f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
; ZVFH-NEXT:    vfabs.v v12, v8
; ZVFH-NEXT:    li a0, 25
; ZVFH-NEXT:    slli a0, a0, 10
; ZVFH-NEXT:    fmv.h.x fa5, a0
; ZVFH-NEXT:    vmflt.vf v0, v12, fa5
; ZVFH-NEXT:    vfcvt.x.f.v v12, v8, v0.t
; ZVFH-NEXT:    vfcvt.f.x.v v12, v12, v0.t
; ZVFH-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
; ZVFH-NEXT:    vfsgnj.vv v8, v12, v8, v0.t
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: rint_nxv16f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT:    lui a0, 307200
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT:    vfabs.v v8, v16
; ZVFHMIN-NEXT:    fmv.w.x fa5, a0
; ZVFHMIN-NEXT:    vmflt.vf v0, v8, fa5
; ZVFHMIN-NEXT:    vfcvt.x.f.v v8, v16, v0.t
; ZVFHMIN-NEXT:    vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
; ZVFHMIN-NEXT:    vfsgnj.vv v16, v8, v16, v0.t
; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT:    ret
  %a = call <vscale x 16 x half> @llvm.rint.nxv16f16(<vscale x 16 x half> %x)
  ret <vscale x 16 x half> %a
}
declare <vscale x 16 x half> @llvm.rint.nxv16f16(<vscale x 16 x half>)

define <vscale x 32 x half> @rint_nxv32f16(<vscale x 32 x half> %x) {
; ZVFH-LABEL: rint_nxv32f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
; ZVFH-NEXT:    vfabs.v v16, v8
; ZVFH-NEXT:    li a0, 25
; ZVFH-NEXT:    slli a0, a0, 10
; ZVFH-NEXT:    fmv.h.x fa5, a0
; ZVFH-NEXT:    vmflt.vf v0, v16, fa5
; ZVFH-NEXT:    vfcvt.x.f.v v16, v8, v0.t
; ZVFH-NEXT:    vfcvt.f.x.v v16, v16, v0.t
; ZVFH-NEXT:    vsetvli zero, zero, e16, m8, ta, mu
; ZVFH-NEXT:    vfsgnj.vv v8, v16, v8, v0.t
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: rint_nxv32f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT:    lui a0, 307200
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT:    vfabs.v v24, v16
; ZVFHMIN-NEXT:    fmv.w.x fa5, a0
; ZVFHMIN-NEXT:    vmflt.vf v0, v24, fa5
; ZVFHMIN-NEXT:    vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT:    vfcvt.f.x.v v24, v24, v0.t
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
; ZVFHMIN-NEXT:    vfsgnj.vv v16, v24, v16, v0.t
; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT:    vfwcvt.f.f.v v24, v12
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT:    vfabs.v v8, v24
; ZVFHMIN-NEXT:    vmflt.vf v0, v8, fa5
; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT:    vfcvt.x.f.v v16, v24, v0.t
; ZVFHMIN-NEXT:    vfcvt.f.x.v v16, v16, v0.t
; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
; ZVFHMIN-NEXT:    vfsgnj.vv v24, v16, v24, v0.t
; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT:    vfncvt.f.f.w v12, v24
; ZVFHMIN-NEXT:    ret
  %a = call <vscale x 32 x half> @llvm.rint.nxv32f16(<vscale x 32 x half> %x)
  ret <vscale x 32 x half> %a
}
declare <vscale x 32 x half> @llvm.rint.nxv32f16(<vscale x 32 x half>)

define <vscale x 1 x float> @rint_nxv1f32(<vscale x 1 x float> %x) {
; CHECK-LABEL: rint_nxv1f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT:    vfabs.v v9, v8
; CHECK-NEXT:    lui a0, 307200
; CHECK-NEXT:    fmv.w.x fa5, a0
; CHECK-NEXT:    vmflt.vf v0, v9, fa5
; CHECK-NEXT:    vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT:    vfcvt.f.x.v v9, v9, v0.t
; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT:    ret
  %a = call <vscale x 1 x float> @llvm.rint.nxv1f32(<vscale x 1 x float> %x)
  ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.rint.nxv1f32(<vscale x 1 x float>)

define <vscale x 2 x float> @rint_nxv2f32(<vscale x 2 x float> %x) {
; CHECK-LABEL: rint_nxv2f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vfabs.v v9, v8
; CHECK-NEXT:    lui a0, 307200
; CHECK-NEXT:    fmv.w.x fa5, a0
; CHECK-NEXT:    vmflt.vf v0, v9, fa5
; CHECK-NEXT:    vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT:    vfcvt.f.x.v v9, v9, v0.t
; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT:    ret
  %a = call <vscale x 2 x float> @llvm.rint.nxv2f32(<vscale x 2 x float> %x)
  ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.rint.nxv2f32(<vscale x 2 x float>)

define <vscale x 4 x float> @rint_nxv4f32(<vscale x 4 x float> %x) {
; CHECK-LABEL: rint_nxv4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT:    vfabs.v v10, v8
; CHECK-NEXT:    lui a0, 307200
; CHECK-NEXT:    fmv.w.x fa5, a0
; CHECK-NEXT:    vmflt.vf v0, v10, fa5
; CHECK-NEXT:    vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT:    vfcvt.f.x.v v10, v10, v0.t
; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
; CHECK-NEXT:    vfsgnj.vv v8, v10, v8, v0.t
; CHECK-NEXT:    ret
  %a = call <vscale x 4 x float> @llvm.rint.nxv4f32(<vscale x 4 x float> %x)
  ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.rint.nxv4f32(<vscale x 4 x float>)

define <vscale x 8 x float> @rint_nxv8f32(<vscale x 8 x float> %x) {
; CHECK-LABEL: rint_nxv8f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT:    vfabs.v v12, v8
; CHECK-NEXT:    lui a0, 307200
; CHECK-NEXT:    fmv.w.x fa5, a0
; CHECK-NEXT:    vmflt.vf v0, v12, fa5
; CHECK-NEXT:    vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT:    vfcvt.f.x.v v12, v12, v0.t
; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
; CHECK-NEXT:    vfsgnj.vv v8, v12, v8, v0.t
; CHECK-NEXT:    ret
  %a = call <vscale x 8 x float> @llvm.rint.nxv8f32(<vscale x 8 x float> %x)
  ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.rint.nxv8f32(<vscale x 8 x float>)

define <vscale x 16 x float> @rint_nxv16f32(<vscale x 16 x float> %x) {
; CHECK-LABEL: rint_nxv16f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT:    vfabs.v v16, v8
; CHECK-NEXT:    lui a0, 307200
; CHECK-NEXT:    fmv.w.x fa5, a0
; CHECK-NEXT:    vmflt.vf v0, v16, fa5
; CHECK-NEXT:    vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT:    vfcvt.f.x.v v16, v16, v0.t
; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
; CHECK-NEXT:    vfsgnj.vv v8, v16, v8, v0.t
; CHECK-NEXT:    ret
  %a = call <vscale x 16 x float> @llvm.rint.nxv16f32(<vscale x 16 x float> %x)
  ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.rint.nxv16f32(<vscale x 16 x float>)

define <vscale x 1 x double> @rint_nxv1f64(<vscale x 1 x double> %x) {
; RV32ZVFH-LABEL: rint_nxv1f64:
; RV32ZVFH:       # %bb.0:
; RV32ZVFH-NEXT:    lui a0, %hi(.LCPI17_0)
; RV32ZVFH-NEXT:    fld fa5, %lo(.LCPI17_0)(a0)
; RV32ZVFH-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV32ZVFH-NEXT:    vfabs.v v9, v8
; RV32ZVFH-NEXT:    vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT:    vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT:    vfcvt.f.x.v v9, v9, v0.t
; RV32ZVFH-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
; RV32ZVFH-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
; RV32ZVFH-NEXT:    ret
;
; RV64ZVFH-LABEL: rint_nxv1f64:
; RV64ZVFH:       # %bb.0:
; RV64ZVFH-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV64ZVFH-NEXT:    vfabs.v v9, v8
; RV64ZVFH-NEXT:    li a0, 1075
; RV64ZVFH-NEXT:    slli a0, a0, 52
; RV64ZVFH-NEXT:    fmv.d.x fa5, a0
; RV64ZVFH-NEXT:    vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT:    vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT:    vfcvt.f.x.v v9, v9, v0.t
; RV64ZVFH-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
; RV64ZVFH-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
; RV64ZVFH-NEXT:    ret
;
; RV32ZVFHMIN-LABEL: rint_nxv1f64:
; RV32ZVFHMIN:       # %bb.0:
; RV32ZVFHMIN-NEXT:    lui a0, %hi(.LCPI17_0)
; RV32ZVFHMIN-NEXT:    fld fa5, %lo(.LCPI17_0)(a0)
; RV32ZVFHMIN-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT:    vfabs.v v9, v8
; RV32ZVFHMIN-NEXT:    vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT:    vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT:    vfcvt.f.x.v v9, v9, v0.t
; RV32ZVFHMIN-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
; RV32ZVFHMIN-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
; RV32ZVFHMIN-NEXT:    ret
;
; RV64ZVFHMIN-LABEL: rint_nxv1f64:
; RV64ZVFHMIN:       # %bb.0:
; RV64ZVFHMIN-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV64ZVFHMIN-NEXT:    vfabs.v v9, v8
; RV64ZVFHMIN-NEXT:    li a0, 1075
; RV64ZVFHMIN-NEXT:    slli a0, a0, 52
; RV64ZVFHMIN-NEXT:    fmv.d.x fa5, a0
; RV64ZVFHMIN-NEXT:    vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT:    vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT:    vfcvt.f.x.v v9, v9, v0.t
; RV64ZVFHMIN-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
; RV64ZVFHMIN-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
; RV64ZVFHMIN-NEXT:    ret
  %a = call <vscale x 1 x double> @llvm.rint.nxv1f64(<vscale x 1 x double> %x)
  ret <vscale x 1 x double> %a
}
declare <vscale x 1 x double> @llvm.rint.nxv1f64(<vscale x 1 x double>)

define <vscale x 2 x double> @rint_nxv2f64(<vscale x 2 x double> %x) {
; RV32ZVFH-LABEL: rint_nxv2f64:
; RV32ZVFH:       # %bb.0:
; RV32ZVFH-NEXT:    lui a0, %hi(.LCPI18_0)
; RV32ZVFH-NEXT:    fld fa5, %lo(.LCPI18_0)(a0)
; RV32ZVFH-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV32ZVFH-NEXT:    vfabs.v v10, v8
; RV32ZVFH-NEXT:    vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT:    vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFH-NEXT:    vfcvt.f.x.v v10, v10, v0.t
; RV32ZVFH-NEXT:    vsetvli zero, zero, e64, m2, ta, mu
; RV32ZVFH-NEXT:    vfsgnj.vv v8, v10, v8, v0.t
; RV32ZVFH-NEXT:    ret
;
; RV64ZVFH-LABEL: rint_nxv2f64:
; RV64ZVFH:       # %bb.0:
; RV64ZVFH-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV64ZVFH-NEXT:    vfabs.v v10, v8
; RV64ZVFH-NEXT:    li a0, 1075
; RV64ZVFH-NEXT:    slli a0, a0, 52
; RV64ZVFH-NEXT:    fmv.d.x fa5, a0
; RV64ZVFH-NEXT:    vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT:    vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFH-NEXT:    vfcvt.f.x.v v10, v10, v0.t
; RV64ZVFH-NEXT:    vsetvli zero, zero, e64, m2, ta, mu
; RV64ZVFH-NEXT:    vfsgnj.vv v8, v10, v8, v0.t
; RV64ZVFH-NEXT:    ret
;
; RV32ZVFHMIN-LABEL: rint_nxv2f64:
; RV32ZVFHMIN:       # %bb.0:
; RV32ZVFHMIN-NEXT:    lui a0, %hi(.LCPI18_0)
; RV32ZVFHMIN-NEXT:    fld fa5, %lo(.LCPI18_0)(a0)
; RV32ZVFHMIN-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV32ZVFHMIN-NEXT:    vfabs.v v10, v8
; RV32ZVFHMIN-NEXT:    vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT:    vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFHMIN-NEXT:    vfcvt.f.x.v v10, v10, v0.t
; RV32ZVFHMIN-NEXT:    vsetvli zero, zero, e64, m2, ta, mu
; RV32ZVFHMIN-NEXT:    vfsgnj.vv v8, v10, v8, v0.t
; RV32ZVFHMIN-NEXT:    ret
;
; RV64ZVFHMIN-LABEL: rint_nxv2f64:
; RV64ZVFHMIN:       # %bb.0:
; RV64ZVFHMIN-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV64ZVFHMIN-NEXT:    vfabs.v v10, v8
; RV64ZVFHMIN-NEXT:    li a0, 1075
; RV64ZVFHMIN-NEXT:    slli a0, a0, 52
; RV64ZVFHMIN-NEXT:    fmv.d.x fa5, a0
; RV64ZVFHMIN-NEXT:    vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT:    vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFHMIN-NEXT:    vfcvt.f.x.v v10, v10, v0.t
; RV64ZVFHMIN-NEXT:    vsetvli zero, zero, e64, m2, ta, mu
; RV64ZVFHMIN-NEXT:    vfsgnj.vv v8, v10, v8, v0.t
; RV64ZVFHMIN-NEXT:    ret
  %a = call <vscale x 2 x double> @llvm.rint.nxv2f64(<vscale x 2 x double> %x)
  ret <vscale x 2 x double> %a
}
declare <vscale x 2 x double> @llvm.rint.nxv2f64(<vscale x 2 x double>)

define <vscale x 4 x double> @rint_nxv4f64(<vscale x 4 x double> %x) {
; RV32ZVFH-LABEL: rint_nxv4f64:
; RV32ZVFH:       # %bb.0:
; RV32ZVFH-NEXT:    lui a0, %hi(.LCPI19_0)
; RV32ZVFH-NEXT:    fld fa5, %lo(.LCPI19_0)(a0)
; RV32ZVFH-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV32ZVFH-NEXT:    vfabs.v v12, v8
; RV32ZVFH-NEXT:    vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT:    vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFH-NEXT:    vfcvt.f.x.v v12, v12, v0.t
; RV32ZVFH-NEXT:    vsetvli zero, zero, e64, m4, ta, mu
; RV32ZVFH-NEXT:    vfsgnj.vv v8, v12, v8, v0.t
; RV32ZVFH-NEXT:    ret
;
; RV64ZVFH-LABEL: rint_nxv4f64:
; RV64ZVFH:       # %bb.0:
; RV64ZVFH-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV64ZVFH-NEXT:    vfabs.v v12, v8
; RV64ZVFH-NEXT:    li a0, 1075
; RV64ZVFH-NEXT:    slli a0, a0, 52
; RV64ZVFH-NEXT:    fmv.d.x fa5, a0
; RV64ZVFH-NEXT:    vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT:    vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFH-NEXT:    vfcvt.f.x.v v12, v12, v0.t
; RV64ZVFH-NEXT:    vsetvli zero, zero, e64, m4, ta, mu
; RV64ZVFH-NEXT:    vfsgnj.vv v8, v12, v8, v0.t
; RV64ZVFH-NEXT:    ret
;
; RV32ZVFHMIN-LABEL: rint_nxv4f64:
; RV32ZVFHMIN:       # %bb.0:
; RV32ZVFHMIN-NEXT:    lui a0, %hi(.LCPI19_0)
; RV32ZVFHMIN-NEXT:    fld fa5, %lo(.LCPI19_0)(a0)
; RV32ZVFHMIN-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV32ZVFHMIN-NEXT:    vfabs.v v12, v8
; RV32ZVFHMIN-NEXT:    vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT:    vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFHMIN-NEXT:    vfcvt.f.x.v v12, v12, v0.t
; RV32ZVFHMIN-NEXT:    vsetvli zero, zero, e64, m4, ta, mu
; RV32ZVFHMIN-NEXT:    vfsgnj.vv v8, v12, v8, v0.t
; RV32ZVFHMIN-NEXT:    ret
;
; RV64ZVFHMIN-LABEL: rint_nxv4f64:
; RV64ZVFHMIN:       # %bb.0:
; RV64ZVFHMIN-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV64ZVFHMIN-NEXT:    vfabs.v v12, v8
; RV64ZVFHMIN-NEXT:    li a0, 1075
; RV64ZVFHMIN-NEXT:    slli a0, a0, 52
; RV64ZVFHMIN-NEXT:    fmv.d.x fa5, a0
; RV64ZVFHMIN-NEXT:    vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT:    vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFHMIN-NEXT:    vfcvt.f.x.v v12, v12, v0.t
; RV64ZVFHMIN-NEXT:    vsetvli zero, zero, e64, m4, ta, mu
; RV64ZVFHMIN-NEXT:    vfsgnj.vv v8, v12, v8, v0.t
; RV64ZVFHMIN-NEXT:    ret
  %a = call <vscale x 4 x double> @llvm.rint.nxv4f64(<vscale x 4 x double> %x)
  ret <vscale x 4 x double> %a
}
declare <vscale x 4 x double> @llvm.rint.nxv4f64(<vscale x 4 x double>)

define <vscale x 8 x double> @rint_nxv8f64(<vscale x 8 x double> %x) {
; RV32ZVFH-LABEL: rint_nxv8f64:
; RV32ZVFH:       # %bb.0:
; RV32ZVFH-NEXT:    lui a0, %hi(.LCPI20_0)
; RV32ZVFH-NEXT:    fld fa5, %lo(.LCPI20_0)(a0)
; RV32ZVFH-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; RV32ZVFH-NEXT:    vfabs.v v16, v8
; RV32ZVFH-NEXT:    vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT:    vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFH-NEXT:    vfcvt.f.x.v v16, v16, v0.t
; RV32ZVFH-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFH-NEXT:    vfsgnj.vv v8, v16, v8, v0.t
; RV32ZVFH-NEXT:    ret
;
; RV64ZVFH-LABEL: rint_nxv8f64:
; RV64ZVFH:       # %bb.0:
; RV64ZVFH-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; RV64ZVFH-NEXT:    vfabs.v v16, v8
; RV64ZVFH-NEXT:    li a0, 1075
; RV64ZVFH-NEXT:    slli a0, a0, 52
; RV64ZVFH-NEXT:    fmv.d.x fa5, a0
; RV64ZVFH-NEXT:    vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT:    vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFH-NEXT:    vfcvt.f.x.v v16, v16, v0.t
; RV64ZVFH-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFH-NEXT:    vfsgnj.vv v8, v16, v8, v0.t
; RV64ZVFH-NEXT:    ret
;
; RV32ZVFHMIN-LABEL: rint_nxv8f64:
; RV32ZVFHMIN:       # %bb.0:
; RV32ZVFHMIN-NEXT:    lui a0, %hi(.LCPI20_0)
; RV32ZVFHMIN-NEXT:    fld fa5, %lo(.LCPI20_0)(a0)
; RV32ZVFHMIN-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT:    vfabs.v v16, v8
; RV32ZVFHMIN-NEXT:    vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT:    vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFHMIN-NEXT:    vfcvt.f.x.v v16, v16, v0.t
; RV32ZVFHMIN-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFHMIN-NEXT:    vfsgnj.vv v8, v16, v8, v0.t
; RV32ZVFHMIN-NEXT:    ret
;
; RV64ZVFHMIN-LABEL: rint_nxv8f64:
; RV64ZVFHMIN:       # %bb.0:
; RV64ZVFHMIN-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT:    vfabs.v v16, v8
; RV64ZVFHMIN-NEXT:    li a0, 1075
; RV64ZVFHMIN-NEXT:    slli a0, a0, 52
; RV64ZVFHMIN-NEXT:    fmv.d.x fa5, a0
; RV64ZVFHMIN-NEXT:    vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT:    vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFHMIN-NEXT:    vfcvt.f.x.v v16, v16, v0.t
; RV64ZVFHMIN-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFHMIN-NEXT:    vfsgnj.vv v8, v16, v8, v0.t
; RV64ZVFHMIN-NEXT:    ret
  %a = call <vscale x 8 x double> @llvm.rint.nxv8f64(<vscale x 8 x double> %x)
  ret <vscale x 8 x double> %a
}
declare <vscale x 8 x double> @llvm.rint.nxv8f64(<vscale x 8 x double>)