; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; Test that libcalls used only by return are tail called.
; This tests non-float libcalls
; RUN: llc -mtriple=hexagon-- -verify-machineinstrs < %s | FileCheck %s

define i32 @udiv(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: udiv:
; CHECK:       // %bb.0:
; CHECK-NEXT:    {
; CHECK-NEXT:     jump __hexagon_udivsi3
; CHECK-NEXT:    }
  %1 = udiv i32 %a, %b
  ret i32 %1
}

define i32 @udivconstby(i32 %a) nounwind {
; CHECK-LABEL: udivconstby:
; CHECK:       // %bb.0:
; CHECK-NEXT:    {
; CHECK-NEXT:     r1:0 = combine(r0,#10)
; CHECK-NEXT:     jump __hexagon_udivsi3
; CHECK-NEXT:    }
  %1 = udiv i32 10, %a
  ret i32 %1
}

define i32 @sdiv(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: sdiv:
; CHECK:       // %bb.0:
; CHECK-NEXT:    {
; CHECK-NEXT:     jump __hexagon_divsi3
; CHECK-NEXT:    }
  %1 = sdiv i32 %a, %b
  ret i32 %1
}

define i32 @sdivconstby(i32 %a) nounwind {
; CHECK-LABEL: sdivconstby:
; CHECK:       // %bb.0:
; CHECK-NEXT:    {
; CHECK-NEXT:     r1:0 = combine(r0,#10)
; CHECK-NEXT:     jump __hexagon_divsi3
; CHECK-NEXT:    }
  %1 = sdiv i32 10, %a
  ret i32 %1
}

define i32 @urem(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: urem:
; CHECK:       // %bb.0:
; CHECK-NEXT:    {
; CHECK-NEXT:     jump __hexagon_umodsi3
; CHECK-NEXT:    }
  %1 = urem i32 %a, %b
  ret i32 %1
}

define i32 @uremconstby(i32 %a) nounwind {
; CHECK-LABEL: uremconstby:
; CHECK:       // %bb.0:
; CHECK-NEXT:    {
; CHECK-NEXT:     r1:0 = combine(r0,#10)
; CHECK-NEXT:     jump __hexagon_umodsi3
; CHECK-NEXT:    }
  %1 = urem i32 10, %a
  ret i32 %1
}

define i32 @srem(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: srem:
; CHECK:       // %bb.0:
; CHECK-NEXT:    {
; CHECK-NEXT:     jump __hexagon_modsi3
; CHECK-NEXT:    }
  %1 = srem i32 %a, %b
  ret i32 %1
}

define i32 @sremconstby(i32 %a) nounwind {
; CHECK-LABEL: sremconstby:
; CHECK:       // %bb.0:
; CHECK-NEXT:    {
; CHECK-NEXT:     r1:0 = combine(r0,#10)
; CHECK-NEXT:     jump __hexagon_modsi3
; CHECK-NEXT:    }
  %1 = srem i32 10, %a
  ret i32 %1
}