From bf835169a52b792acc9f8ad26141fb3e556b6f71 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Fri, 19 Sep 2025 20:15:38 +0300 Subject: [AArch64] Remove post-decoding instruction mutations (#156364) Add `bits<0>` fields to instructions using the ZTR/MPR/MPR8 register classes. These register classes contain only one register, and it is not encoded in the instruction. This way, the generated decoder can completely decode instructions without having to perform a post-decoding pass to insert missing operands. Some immediate operands are also not encoded and have only one possible value "zero". Use this trick for them, too. Finally, remove `-ignore-non-decodable-operands` option from `llvm-tblgen` invocation to ensure that non-decodable operands do not appear in the future. --- utils/bazel/llvm-project-overlay/llvm/BUILD.bazel | 1 - 1 file changed, 1 deletion(-) (limited to 'utils') diff --git a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel index 8fe8258d72e3..22f80efb8ad4 100644 --- a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel @@ -2249,7 +2249,6 @@ llvm_target_lib_list = [lib for lib in [ "lib/Target/ARM/ARMGenSubtargetInfo.inc": ["-gen-subtarget"], "lib/Target/ARM/ARMGenDisassemblerTables.inc": [ "-gen-disassembler", - "-ignore-non-decodable-operands", ], }, }, -- cgit v1.2.3