From e7107973b83b7053f3ba92a40a33a27db0c90529 Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Sat, 22 Mar 2025 11:07:48 +0530 Subject: Recommit "[RISCV] Add Qualcomm uC Xqcisync (Sync Delay) extension (#132184)" (#132520) With a minor fix for the build failures. Original message: This extension adds nine instructions, eight for non-memory-mapped devices synchronization and delay instruction. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0 This patch adds assembler only support. Co-authored-by: Sudharsan Veeravalli quic_svs@quicinc.com --- .../RISCV/Disassembler/RISCVDisassembler.cpp | 26 +++++++++++++++------- 1 file changed, 18 insertions(+), 8 deletions(-) (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp') diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 5abf15a..93cbf66 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -370,6 +370,15 @@ static DecodeStatus decodeUImmPlus1OperandGE(MCInst &Inst, uint32_t Imm, return MCDisassembler::Success; } +static DecodeStatus decodeUImmSlistOperand(MCInst &Inst, uint32_t Imm, + int64_t Address, + const MCDisassembler *Decoder) { + assert(isUInt<3>(Imm) && "Invalid Slist immediate"); + const uint8_t Slist[] = {0, 1, 2, 4, 8, 16, 15, 31}; + Inst.addOperand(MCOperand::createImm(Slist[Imm])); + return MCDisassembler::Success; +} + static DecodeStatus decodeUImmLog2XLenOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder) { @@ -663,14 +672,15 @@ static constexpr FeatureBitset XRivosFeatureGroup = { }; static constexpr FeatureBitset XqciFeatureGroup = { - RISCV::FeatureVendorXqcia, RISCV::FeatureVendorXqciac, - RISCV::FeatureVendorXqcibi, RISCV::FeatureVendorXqcibm, - RISCV::FeatureVendorXqcicli, RISCV::FeatureVendorXqcicm, - RISCV::FeatureVendorXqcics, RISCV::FeatureVendorXqcicsr, - RISCV::FeatureVendorXqciint, RISCV::FeatureVendorXqcilb, - RISCV::FeatureVendorXqcili, RISCV::FeatureVendorXqcilia, - RISCV::FeatureVendorXqcilo, RISCV::FeatureVendorXqcilsm, - RISCV::FeatureVendorXqcisim, RISCV::FeatureVendorXqcisls, + RISCV::FeatureVendorXqcia, RISCV::FeatureVendorXqciac, + RISCV::FeatureVendorXqcibi, RISCV::FeatureVendorXqcibm, + RISCV::FeatureVendorXqcicli, RISCV::FeatureVendorXqcicm, + RISCV::FeatureVendorXqcics, RISCV::FeatureVendorXqcicsr, + RISCV::FeatureVendorXqciint, RISCV::FeatureVendorXqcilb, + RISCV::FeatureVendorXqcili, RISCV::FeatureVendorXqcilia, + RISCV::FeatureVendorXqcilo, RISCV::FeatureVendorXqcilsm, + RISCV::FeatureVendorXqcisim, RISCV::FeatureVendorXqcisls, + RISCV::FeatureVendorXqcisync, }; static constexpr FeatureBitset XSfVectorGroup = { -- cgit v1.1