From d50bb3c8d4cad23d694e8fa96d0e22bf659894d3 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Thu, 5 Sep 2013 18:37:52 +0000 Subject: R600/SI: Don't emit S_WQM_B64 instruction for compute shaders llvm-svn: 190077 --- llvm/lib/Target/R600/SILowerControlFlow.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'llvm/lib/Target/R600/SILowerControlFlow.cpp') diff --git a/llvm/lib/Target/R600/SILowerControlFlow.cpp b/llvm/lib/Target/R600/SILowerControlFlow.cpp index c2e8f02..09cf25b 100644 --- a/llvm/lib/Target/R600/SILowerControlFlow.cpp +++ b/llvm/lib/Target/R600/SILowerControlFlow.cpp @@ -409,6 +409,7 @@ void SILowerControlFlowPass::IndirectDst(MachineInstr &MI) { bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) { TII = MF.getTarget().getInstrInfo(); TRI = MF.getTarget().getRegisterInfo(); + SIMachineFunctionInfo *MFI = MF.getInfo(); bool HaveKill = false; bool NeedM0 = false; @@ -508,7 +509,7 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) { AMDGPU::M0).addImm(0xffffffff); } - if (NeedWQM) { + if (NeedWQM && MFI->ShaderType != ShaderType::COMPUTE) { MachineBasicBlock &MBB = MF.front(); BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_WQM_B64), AMDGPU::EXEC).addReg(AMDGPU::EXEC); -- cgit v1.1