From 024a623c5599bd11839939dfed0eeecbc389201e Mon Sep 17 00:00:00 2001 From: Chuang-Yu Cheng Date: Wed, 6 Apr 2016 01:47:02 +0000 Subject: [Power9] Implement add-pc, multiply-add, modulo, extend-sign-shift, random number, set bool, and dfp test significance This patch implement the following instructions: - addpcis subpcis - maddhd maddhdu maddld - modsw moduw modsd modud - darn - extswsli extswsli. - setb - dtstsfi dtstsfiq Total 15 instructions Reviewers: nemanjai hfinkel tjablin amehsan kbarton http://reviews.llvm.org/D17885 llvm-svn: 265505 --- llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp') diff --git a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp index 6ea4fb1..35ff3b9 100644 --- a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp +++ b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp @@ -242,6 +242,12 @@ static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, return decodeRegisterClass(Inst, RegNo, FRegs); } +static DecodeStatus DecodeD8RCRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + return decodeRegisterClass(Inst, RegNo, FRegs); +} + static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { -- cgit v1.1