From ba532dc81648aca4cdf9ba4f5f16ecbc971e811c Mon Sep 17 00:00:00 2001 From: Kit Barton Date: Tue, 8 Mar 2016 03:49:13 +0000 Subject: [Power9] Implement new vsx instructions: load, store instructions for vector and scalar We follow the comments mentioned in http://reviews.llvm.org/D16842#344378 to implement this new patch. This patch implements the following vsx instructions: Vector load/store: lxv lxvx lxvb16x lxvl lxvll lxvh8x lxvwsx stxv stxvb16x stxvh8x stxvl stxvll stxvx Scalar load/store: lxsd lxssp lxsibzx lxsihzx stxsd stxssp stxsibx stxsihx 21 instructions Phabricator: http://reviews.llvm.org/D16919 llvm-svn: 262906 --- llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp | 3 +++ 1 file changed, 3 insertions(+) (limited to 'llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp') diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp index a0b15d5..032112c 100644 --- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp +++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp @@ -492,6 +492,9 @@ public: bool isS16ImmX4() const { return Kind == Expression || (Kind == Immediate && isInt<16>(getImm()) && (getImm() & 3) == 0); } + bool isS16ImmX16() const { return Kind == Expression || + (Kind == Immediate && isInt<16>(getImm()) && + (getImm() & 15) == 0); } bool isS17Imm() const { switch (Kind) { case Expression: -- cgit v1.1