From d9790793d60978c72436a588204130d7be09a04f Mon Sep 17 00:00:00 2001 From: Zoran Jovanovic Date: Wed, 9 Sep 2015 09:10:46 +0000 Subject: [mips][microMIPS] Implement CACHEE and PREFE instructions Differential Revision: http://reviews.llvm.org/D11628 llvm-svn: 247125 --- .../Target/Mips/Disassembler/MipsDisassembler.cpp | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp') diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index cbf9e13..c51a4f0 100644 --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -261,6 +261,11 @@ static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus DecodePrefeOpMM(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, @@ -1152,6 +1157,23 @@ static DecodeStatus DecodeCacheOpMM(MCInst &Inst, return MCDisassembler::Success; } +static DecodeStatus DecodePrefeOpMM(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder) { + int Offset = SignExtend32<9>(Insn & 0x1ff); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + unsigned Hint = fieldFromInstruction(Insn, 21, 5); + + Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + + Inst.addOperand(MCOperand::createReg(Base)); + Inst.addOperand(MCOperand::createImm(Offset)); + Inst.addOperand(MCOperand::createImm(Hint)); + + return MCDisassembler::Success; +} + static DecodeStatus DecodeCacheOpR6(MCInst &Inst, unsigned Insn, uint64_t Address, -- cgit v1.1