From ff370ed90e711e87c028bdedd97007809decb16c Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Fri, 26 Dec 2014 20:30:58 +0000 Subject: [Hexagon] Adding deallocframe and circular addressing loads. llvm-svn: 224869 --- .../Hexagon/Disassembler/HexagonDisassembler.cpp | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp') diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp index 3106317..015efea 100644 --- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -49,6 +49,8 @@ public: }; } +static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, const void *Decoder); static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); @@ -105,6 +107,23 @@ static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, return MCDisassembler::Success; } +static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t /*Address*/, const void *Decoder) { + unsigned Register = 0; + switch (RegNo) { + case 0: + Register = Hexagon::M0; + break; + case 1: + Register = Hexagon::M1; + break; + default: + return MCDisassembler::Fail; + } + Inst.addOperand(MCOperand::CreateReg(Register)); + return MCDisassembler::Success; +} + static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { static const uint16_t DoubleRegDecoderTable[] = { -- cgit v1.1