From df24da221eecb5f106d7e9c4fa3a7bf8ab09c1ad Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Thu, 22 Dec 2016 18:49:55 +0000 Subject: Fix two bugs in the pipeliner in renaming phis in the prolog and epilog When the pipeliner is renaming phi values, it may need to iterate through the phi operands to check for other phis. However, the pipeliner should stop once it reaches a phi that is outside the pipelined loop. Also, when the generateExistingPhis code is unable to reuse an existing phi, the default code that computes the PhiOp2 is only to be used when the pipeliner is generating the kernel. Otherwise, the phi may be a value computed earlier in the same epilog. Patch by Brendon Cahoon. llvm-svn: 290355 --- llvm/lib/CodeGen/MachinePipeliner.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'llvm/lib/CodeGen/MachinePipeliner.cpp') diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp index c908681..d9528cd 100644 --- a/llvm/lib/CodeGen/MachinePipeliner.cpp +++ b/llvm/lib/CodeGen/MachinePipeliner.cpp @@ -2676,7 +2676,7 @@ void SwingSchedulerDAG::generateExistingPhis( replaceRegUsesAfterLoop(Def, NewReg, BB, MRI, LIS); continue; } - } else if (StageDiff > 0 && + } else if (InKernel && StageDiff > 0 && VRMap[CurStageNum - StageDiff - np].count(LoopVal)) PhiOp2 = VRMap[CurStageNum - StageDiff - np][LoopVal]; } @@ -3216,7 +3216,7 @@ unsigned SwingSchedulerDAG::getPrevMapVal(unsigned StageNum, unsigned PhiStage, // The previous name is defined in the current stage when the instruction // order is swapped. PrevVal = VRMap[StageNum][LoopVal]; - else if (!LoopInst->isPHI()) + else if (!LoopInst->isPHI() || LoopInst->getParent() != BB) // The loop value hasn't yet been scheduled. PrevVal = LoopVal; else if (StageNum == PhiStage + 1) -- cgit v1.1