From 12bdcab59c7ed91475b2f9cd25f45e72b5d1f9f1 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Wed, 11 Oct 2017 15:59:51 +0000 Subject: [Pipeliner] Fix offset value for instrs dependent on post-inc load/stores The software pipeliner and the packetizer try to break dependence between the post-increment instruction and the dependent memory instructions by changing the base register and the offset value. However, in some cases, the existing logic didn't work properly and created incorrect offset value. Patch by Jyotsna Verma. llvm-svn: 315468 --- llvm/lib/CodeGen/MachinePipeliner.cpp | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'llvm/lib/CodeGen/MachinePipeliner.cpp') diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp index 20141f7..c852c2e 100644 --- a/llvm/lib/CodeGen/MachinePipeliner.cpp +++ b/llvm/lib/CodeGen/MachinePipeliner.cpp @@ -3892,9 +3892,14 @@ void SwingSchedulerDAG::fixupRegisterOverlaps(std::deque &Instrs) { unsigned BasePos, OffsetPos; // Update the base register and adjust the offset. if (TII->getBaseAndOffsetPosition(*MI, BasePos, OffsetPos)) { - MI->getOperand(BasePos).setReg(NewBaseReg); - int64_t Offset = MI->getOperand(OffsetPos).getImm(); - MI->getOperand(OffsetPos).setImm(Offset - It->second.second); + MachineInstr *NewMI = MF.CloneMachineInstr(MI); + NewMI->getOperand(BasePos).setReg(NewBaseReg); + int64_t NewOffset = + MI->getOperand(OffsetPos).getImm() - It->second.second; + NewMI->getOperand(OffsetPos).setImm(NewOffset); + SU->setInstr(NewMI); + MISUnitMap[NewMI] = SU; + NewMIs.insert(NewMI); } } OverlapReg = 0; -- cgit v1.1