From 9d419d3b0cfda0f85d88633bd8620cd65ccb0498 Mon Sep 17 00:00:00 2001
From: Francis Visoiu Mistrih <francisvm@yahoo.com>
Date: Tue, 28 Nov 2017 12:42:37 +0000
Subject: [CodeGen] Rename functions PrintReg* to printReg*

LLVM Coding Standards:
  Function names should be verb phrases (as they represent actions), and
  command-like function should be imperative. The name should be camel
  case, and start with a lower case letter (e.g. openFile() or isFoo()).

Differential Revision: https://reviews.llvm.org/D40416

llvm-svn: 319168
---
 llvm/lib/CodeGen/MachineInstr.cpp | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'llvm/lib/CodeGen/MachineInstr.cpp')

diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 26b4402..2d5307c 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -391,7 +391,7 @@ void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
                            const TargetIntrinsicInfo *IntrinsicInfo) const {
   switch (getType()) {
   case MachineOperand::MO_Register:
-    OS << PrintReg(getReg(), TRI, getSubReg());
+    OS << printReg(getReg(), TRI, getSubReg());
 
     if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
         isInternalRead() || isEarlyClobber() || isTied()) {
@@ -520,7 +520,7 @@ void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
       if (getRegMask()[MaskWord] & (1 << MaskBit)) {
         if (PrintRegMaskNumRegs < 0 ||
             NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
-          OS << " " << PrintReg(i, TRI);
+          OS << " " << printReg(i, TRI);
           NumRegsEmitted++;
         }
         NumRegsInMask++;
@@ -2123,14 +2123,14 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
       else
         OS << " "
            << TRI->getRegClassName(RC.get<const TargetRegisterClass *>());
-      OS << ':' << PrintReg(VirtRegs[i]);
+      OS << ':' << printReg(VirtRegs[i]);
       for (unsigned j = i+1; j != VirtRegs.size();) {
         if (MRI->getRegClassOrRegBank(VirtRegs[j]) != RC) {
           ++j;
           continue;
         }
         if (VirtRegs[i] != VirtRegs[j])
-          OS << "," << PrintReg(VirtRegs[j]);
+          OS << "," << printReg(VirtRegs[j]);
         VirtRegs.erase(VirtRegs.begin()+j);
       }
     }
-- 
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