From ce7fd498ed91344c23f0864bbd5b84d65eaae3ef Mon Sep 17 00:00:00 2001 From: Christudasan Devadasan Date: Thu, 16 Nov 2023 10:30:03 +0530 Subject: [AMDGPU] RA inserted scalar instructions can be at the BB top (#72140) We adjust the insertion point at the BB top for spills/copies during RA to ensure they are placed after the exec restore instructions required for the divergent control flow execution. This is, however, required only for the vector operations. The insertions for scalar registers can still go to the BB top. --- llvm/lib/CodeGen/MachineBasicBlock.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'llvm/lib/CodeGen/MachineBasicBlock.cpp') diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp index d9e2268..4410fb7 100644 --- a/llvm/lib/CodeGen/MachineBasicBlock.cpp +++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp @@ -223,13 +223,13 @@ MachineBasicBlock::SkipPHIsAndLabels(MachineBasicBlock::iterator I) { MachineBasicBlock::iterator MachineBasicBlock::SkipPHIsLabelsAndDebug(MachineBasicBlock::iterator I, - bool SkipPseudoOp) { + Register Reg, bool SkipPseudoOp) { const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo(); iterator E = end(); while (I != E && (I->isPHI() || I->isPosition() || I->isDebugInstr() || (SkipPseudoOp && I->isPseudoProbe()) || - TII->isBasicBlockPrologue(*I))) + TII->isBasicBlockPrologue(*I, Reg))) ++I; // FIXME: This needs to change if we wish to bundle labels / dbg_values // inside the bundle. -- cgit v1.1