From e94a518a22db4b21f4a4a9e34173a11e9dfc5fcc Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Tue, 11 Mar 2014 10:48:52 +0000 Subject: IR: add a second ordering operand to cmpxhg for failure The syntax for "cmpxchg" should now look something like: cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic where the second ordering argument gives the required semantics in the case that no exchange takes place. It should be no stronger than the first ordering constraint and cannot be either "release" or "acq_rel" (since no store will have taken place). rdar://problem/15996804 llvm-svn: 203559 --- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp') diff --git a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp index 8a09507..d390eed 100644 --- a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp +++ b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp @@ -1441,9 +1441,11 @@ static void WriteInstruction(const Instruction &I, unsigned InstID, pushValue(I.getOperand(2), InstID, Vals, VE); // newval. Vals.push_back(cast(I).isVolatile()); Vals.push_back(GetEncodedOrdering( - cast(I).getOrdering())); + cast(I).getSuccessOrdering())); Vals.push_back(GetEncodedSynchScope( cast(I).getSynchScope())); + Vals.push_back(GetEncodedOrdering( + cast(I).getFailureOrdering())); break; case Instruction::AtomicRMW: Code = bitc::FUNC_CODE_INST_ATOMICRMW; -- cgit v1.1