From 778cf5431cafc243f81dd5c8cbd27701ff7f9120 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 2 Nov 2022 18:50:48 -0700 Subject: IR: Add atomicrmw uinc_wrap and udec_wrap These are essentially add/sub 1 with a clamping value. AMDGPU has instructions for these. CUDA/HIP expose these as atomicInc/atomicDec. Currently we use target intrinsics for these, but those do no carry the ordering and syncscope. Add these to atomicrmw so we can carry these and benefit from the regular legalization processes. --- llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp') diff --git a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp index 0a346e3..f014521 100644 --- a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp +++ b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp @@ -1256,6 +1256,10 @@ static AtomicRMWInst::BinOp getDecodedRMWOperation(unsigned Val) { case bitc::RMW_FSUB: return AtomicRMWInst::FSub; case bitc::RMW_FMAX: return AtomicRMWInst::FMax; case bitc::RMW_FMIN: return AtomicRMWInst::FMin; + case bitc::RMW_UINC_WRAP: + return AtomicRMWInst::UIncWrap; + case bitc::RMW_UDEC_WRAP: + return AtomicRMWInst::UDecWrap; } } -- cgit v1.1