From 6e49f73825f1b9cb98352a7c8dca3e0cf83ebd9e Mon Sep 17 00:00:00 2001 From: Jonathan Thackray Date: Wed, 30 Apr 2025 22:06:37 +0100 Subject: Reland [llvm] Add support for llvm IR atomicrmw fminimum/fmaximum instructions (#137701) This patch adds support for LLVM IR atomicrmw `fmaximum` and `fminimum` instructions. These mirror the `llvm.maximum.*` and `llvm.minimum.*` instructions, but are atomic and use IEEE754 2019 handling for NaNs, which is different to `fmax` and `fmin`. See: https://llvm.org/docs/LangRef.html#llvm-minimum-intrinsic for more details. Future changes will allow this LLVM IR to be lowered to specialised assembler instructions on suitable targets, such as AArch64. --- llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp') diff --git a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp index 1d7aa18..0e75c44 100644 --- a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp +++ b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp @@ -1356,6 +1356,10 @@ static AtomicRMWInst::BinOp getDecodedRMWOperation(unsigned Val) { case bitc::RMW_FSUB: return AtomicRMWInst::FSub; case bitc::RMW_FMAX: return AtomicRMWInst::FMax; case bitc::RMW_FMIN: return AtomicRMWInst::FMin; + case bitc::RMW_FMAXIMUM: + return AtomicRMWInst::FMaximum; + case bitc::RMW_FMINIMUM: + return AtomicRMWInst::FMinimum; case bitc::RMW_UINC_WRAP: return AtomicRMWInst::UIncWrap; case bitc::RMW_UDEC_WRAP: -- cgit v1.1