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2024-09-20[mlir][AMDGPU] New gfx12 barrier instructions and update lowering LDSBarrierO...Daniel Hernandez-Juarez1-20/+28
2024-09-19[mlir][vector][xegpu] Vector to XeGPU conversion pass (#107419)Adam Siemieniuk3-0/+274
2024-09-17[mlir][GPU] block_id has the grid size as its rangeBenjamin Kramer1-1/+1
2024-09-16[MLIR] Add f6E2M3FN type (#107999)Sergey Kozub1-1/+1
2024-09-13[mlir][GPU] Plumb range information through the NVVM lowerings (#107659)Krzysztof Drewniak1-16/+38
2024-09-12[mlir][AMDGPU] Remove an old bf16 workaround (#108409)Krzysztof Drewniak1-12/+17
2024-09-12[MLIR][ROCDL] Add dynamically legal ops to LowerGpuOpsToROCDLOpsPass (#108302)Nirvedh Meshram1-1/+7
2024-09-12[mlir][AMDGPU] Enable emulating vector buffer_atomic_fadd on gfx11 (#108312)Krzysztof Drewniak1-2/+0
2024-09-12[mlir][LLVM] Refactor how range() annotations are handled for ROCDL intrinsic...Krzysztof Drewniak1-3/+3
2024-09-11[mlir][AMDGPU] Support vector<2xf16> inputs to buffer atomic fadd (#108286)Krzysztof Drewniak1-2/+5
2024-09-11Update legalizations for LowerGpuOpsToROCDLOps (#108266)Nirvedh Meshram1-4/+3
2024-09-11Revert "[mlir][AMDGPU] Support vector<2xf16> inputs to buffer atomic fadd (#1...Krzysztof Drewniak1-5/+2
2024-09-11[mlir][AMDGPU] Support vector<2xf16> inputs to buffer atomic fadd (#108238)Krzysztof Drewniak1-2/+5
2024-09-11[MLIR][TOSA] add additional verification to TOSA (#108133)Arteen Abrishami1-9/+12
2024-09-11[mlir][vector] Support for extracting 1-element vectors in VectorExtractOpCon...Longsheng Mou1-1/+4
2024-09-11[mlir] Add dependent TensorDialect to ConvertVectorToLLVM pass (#108045)Longsheng Mou1-0/+2
2024-09-10[TOSA] tosa.negate operator lowering update (#107924)Dmitriy Smirnov1-17/+22
2024-09-10[MLIR] Add f6E3M2FN type (#105573)Sergey Kozub1-1/+2
2024-09-09[mlir][amdgpu] Align Chipset with TargetParser (#107720)Jakub Kuderski2-20/+21
2024-09-06[mlir] [scf] fix crash when conversion from scf to control flow (#107221)donald chen1-1/+4
2024-09-04[MLIR][ROCDL] Remove patterns for ops supported as intrinsics in the AMDGPU b...Jan Leyonberg1-8/+6
2024-09-04[mlir][TensorToSPIRV] Add type check for `tensor.extract` in TensorToSPIRV (#...Longsheng Mou1-0/+2
2024-09-03[MLIR][AMDGPU] Add support for fp8 ops on gfx12 (#106388)Giuseppe Rossini1-22/+31
2024-09-02[mlir][ArmSME] Rename slice move operations to insert/extract_tile_slice (#10...Benjamin Maxwell4-72/+69
2024-08-29[mlir][ArmSME] Merge consecutive `arm_sme.intr.zero` ops (#106215)Benjamin Maxwell1-0/+36
2024-08-28[mlir] fix missing LLVMDialect dependency for MLIRSCFToControlFlowChristopher Bate1-0/+1
2024-08-28Reapply "[mlir] NFC: fix dependence of (Tensor|Linalg|MemRef|Complex) dialect...Christopher Bate6-14/+2
2024-08-27[mlir][spirv] Integrate `convert-to-spirv` into `mlir-vulkan-runner` (#106082)Angel Zhang2-31/+70
2024-08-27[mlir][vector] Rename LowerVectorToLLVM to ConvertVectorToLLVM (NFC) (#104785)Hugo Trachino1-3/+3
2024-08-26[MLIR][AMDGPU] Introduce fp16 packed arithmetic (#105688)Giuseppe Rossini2-7/+113
2024-08-23[mlir][Transforms][NFC] Move `ReconcileUnrealizedCasts` implementation (#104671)Matthias Springer1-56/+4
2024-08-21[MLIR][OpenMP] Add missing OpenMP to LLVM conversion patterns (#104440)Sergio Afonso1-31/+38
2024-08-21[MLIR][MathDialect] fix fp32 promotion crash when encounters scf.if (#104451)Ivy Zhang1-0/+1
2024-08-20[mlir][gpu] Add extra value types for gpu::ShuffleOp (#104605)Finlay1-10/+20
2024-08-20[mlir][gpu] Add 'cluster_size' attribute to gpu.subgroup_reduce (#104851)Andrea Faulds2-0/+8
2024-08-20[mlir][spirv] Support `gpu` in `convert-to-spirv` pass (#105010)Angel Zhang2-0/+3
2024-08-20[mlir][EmitC] Model lvalues as a type in EmitC (#91475)Simon Camphausen2-11/+32
2024-08-20[mlir][EmitC] Do not convert illegal types in EmitC (#104571)Longsheng Mou1-3/+3
2024-08-20Revert "[mlir] NFC: fix dependence of (Tensor|Linalg|MemRef|Complex) dialects...Christopher Bate6-4/+20
2024-08-19[mlir] NFC: fix dependence of (Tensor|Linalg|MemRef|Complex) dialects on LLVM...Christopher Bate6-20/+4
2024-08-19[mlir][[spirv] Add support for math.log2 and math.log10 to GLSL/OpenCL SPIRV ...meehatpa1-0/+63
2024-08-16[mlir][emitc] Add 'emitc.switch' op to the dialect (#102331)Andrey Timonin1-15/+55
2024-08-16[mlir][AMDGPU] Implement AMDGPU DPP operation in MLIR. (#89233)stefankoncarevic1-3/+153
2024-08-16[MLIR][GPU-LLVM] Add GPU to LLVM-SPV address space mapping (#102621)Victor Perez3-3/+43
2024-08-13[mlir][GPU] Improve `gpu.module` op implementation (#102866)Matthias Springer3-16/+3
2024-08-12Enable attaching LLVM loop annotations to scf.for (#102562)xiaoleis-nv1-3/+13
2024-08-12[mlir][vector] Add scalable lowering for `transfer_write(transpose)` (#101353)Benjamin Maxwell1-18/+214
2024-08-12[mlir][spirv] Add atan and atan2 pattern to MathToSPIRV Conversion pass (#102...meehatpa1-0/+3
2024-08-09[mlir][spirv] Support `memref` in `convert-to-spirv` pass (#102534)Angel Zhang2-0/+14
2024-08-09[MLIR][GPU-LLVM] Convert `gpu.func` to `llvm.func` (#101664)Victor Perez11-115/+286
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