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2016-09-13Revert of r281304 as it is causing build bot failures in hexagonSjoerd Meijer2-2/+0
hwloop regression tests. These tests pass locally; will be investigating where these differences come from. llvm-svn: 281306
2016-09-13This adds a new field isAdd to MCInstrDesc. The ARM and Hexagon instructionSjoerd Meijer2-0/+2
descriptions now tag add instructions, and the Hexagon backend is using this to identify loop induction statements. Patch by Sam Parker and Sjoerd Meijer. Differential Revision: https://reviews.llvm.org/D23601 llvm-svn: 281304
2016-09-08[TableGen] AsmMatcher: Add AsmVariantName to Instruction class.Sam Kolton1-0/+11
Summary: This allows specifying instructions that are available only in specific assembler variant. If AsmVariantName is specified then instruction will be presented only in MatchTable for this variant. If not specified then assembler variants will be determined based on AsmString. Also this allows splitting assembler match tables in same way as it is done in dissasembler. Reviewers: ab, tstellarAMD, craig.topper, vpykhtin Subscribers: wdng Differential Revision: https://reviews.llvm.org/D24249 llvm-svn: 280952
2016-08-26TableGen: Switch from a std::map to a DenseMap in CodeGenSubRegIndex. NFCJustin Bogner1-2/+1
This mapping is between pointers, which DenseMap is particularly good at. Most targets aren't really affected, but if there's a lot of subregister composition this can shave off a good chunk of time from generating registers. llvm-svn: 279875
2016-08-22[X86] Create a new instruction format to handle 4VOp3 encoding. This saves ↵Craig Topper2-18/+25
one bit in TSFlags and simplifies MRMSrcMem/MRMSrcReg format handling. llvm-svn: 279424
2016-08-22[X86] Create a new instruction format to handle MemOp4 encoding. This saves ↵Craig Topper2-17/+28
one bit in TSFlags and simplifies MRMSrcMem/MRMSrcReg format handling. llvm-svn: 279423
2016-08-22[X86] Space out the encodings of X86 instruction formats. I plan to add some ↵Craig Topper1-83/+83
new encodings in future commits and this will reduce the size of those commits. NFC This tries to keep all the ModRM memory and register forms in their own regions of the encodings. Hoping to make it simple on some of the switch statements that operate on these encodings. llvm-svn: 279422
2016-08-22[X86] Merge small helper function into the switch that calls it since they ↵Craig Topper1-17/+9
both operate on the same variable. NFC llvm-svn: 279421
2016-08-22[X86] Explicitly list all X86 instruction forms in switch statement so its ↵Craig Topper1-1/+10
easier to detect when one is missing. NFC llvm-svn: 279420
2016-08-17Replace a few more "fall through" comments with LLVM_FALLTHROUGHJustin Bogner1-4/+4
Follow up to r278902. I had missed "fall through", with a space. llvm-svn: 278970
2016-08-12Use the range variant of remove_if instead of unpacking begin/endDavid Majnemer2-58/+41
No functionality change is intended. llvm-svn: 278475
2016-08-12Use the range variant of find/find_if instead of unpacking begin/endDavid Majnemer4-27/+11
If the result of the find is only used to compare against end(), just use is_contained instead. No functionality change is intended. llvm-svn: 278469
2016-08-12Use the range variant of find_if instead of unpacking begin/endDavid Majnemer2-16/+11
No functionality change is intended. llvm-svn: 278443
2016-08-11Use the range variant of find instead of unpacking begin/endDavid Majnemer6-19/+11
If the result of the find is only used to compare against end(), just use is_contained instead. No functionality change is intended. llvm-svn: 278433
2016-08-11Use range algorithms instead of unpacking begin/endDavid Majnemer1-8/+7
No functionality change is intended. llvm-svn: 278417
2016-07-27[mips][ias] Check '$rs = $rd' constraints when both registers are in AsmText.Daniel Sanders1-2/+17
Summary: This is one possible solution to the problem of ignoring constraints that Simon raised in D21473 but it's a bit of a hack. The integrated assembler currently ignores violations of the tied register constraints when the operands involved in a tie are both present in the AsmText. For example, 'dati $rs, $rt, $imm' with the '$rs = $rt' will silently replace $rt with $rs. So 'dati $2, $3, 1' is processed as if the user provided 'dati $2, $2, 1' without any diagnostic being emitted. This is difficult to solve properly because there are multiple parts of the matcher that are silently forcing these constraints to be met. Tied operands are rendered to instructions by cloning previously rendered operands but this is unnecessary because the matcher was already instructed to render the operand it would have cloned. This is also unnecessary because earlier code has already replaced the MCParsedOperand with the one it was tied to (so the parsed input is matched as if it were 'dati <RegIdx 2>, <RegIdx 2>, <Imm 1>'). As a result, it looks like fixing this properly amounts to a rewrite of the tied operand handling which affects all targets. This patch however, merely inserts a checking hook just before the substitution of MCParsedOperands and the Mips target overrides it. It's not possible to accurately check the registers are the same this early (because numeric registers haven't been bound to a register class yet) so it cheats a bit and checks that the tokens that produced the operand are lexically identical. This works because tied registers need to have the same register class but it does have a flaw. It will reject 'dati $4, $a0, 1' for violating the constraint even though $a0 ends up as the same register as $4. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: https://reviews.llvm.org/D21994 llvm-svn: 276867
2016-07-26[tblgen] Compare const char * with strcmp instead of creating StringRef.Benjamin Kramer1-2/+2
Avoids a call to strlen on both strings which always reads the entire string. strcmp can use early exit. llvm-svn: 276737
2016-07-20GlobalISel: Remove explicit enumerator values from .def file.Tim Northover1-1/+1
They were all auto-incremented from 0 anyway, and I'm getting really annoying conflicts and runtime failures when different people add more for GlobalISel (and even when I'm refactoring my own patches). NFC. llvm-svn: 276204
2016-07-18TableGen: Allow custom register operand decoder methodMatt Arsenault1-25/+33
This is for a situation where the encoding for a register may be different depending on the specific operand. For some instructions, we want to apply additional restrictions beyond the encoding's constraints. In AMDGPU some operands are VSrc_32, using the VS_32 pseudo register class which accept VGPRs, SGPRs, or immediates in the encoding. Some specific instructions with the same encoding operand do not want to allow immediates or SGPRs, but the encoding format is different in this case than a regular VGPR_32 operand. This allows specifying the encoding should be treated the same without introducing yet another dummy register class. llvm-svn: 275929
2016-07-15IR: Sort generic intrinsics before target specific onesJustin Bogner5-39/+78
This splits out the intrinsic table such that generic intrinsics come first and target specific intrinsics are grouped by target. From here we can find out which target an intrinsic is for or differentiate between generic and target intrinsics. The motivation here is to make it easier to move target specific intrinsic handling out of generic code. llvm-svn: 275575
2016-07-14TableGen: Fix a confusing use of both i and I as variables. NFCJustin Bogner1-5/+5
llvm-svn: 275450
2016-07-14XRay: Add entry and exit sledsDean Michael Berris1-3/+3
Summary: In this patch we implement the following parts of XRay: - Supporting a function attribute named 'function-instrument' which currently only supports 'xray-always'. We should be able to use this attribute for other instrumentation approaches. - Supporting a function attribute named 'xray-instruction-threshold' used to determine whether a function is instrumented with a minimum number of instructions (IR instruction counts). - X86-specific nop sleds as described in the white paper. - A machine function pass that adds the different instrumentation marker instructions at a very late stage. - A way of identifying which return opcode is considered "normal" for each architecture. There are some caveats here: 1) We don't handle PATCHABLE_RET in platforms other than x86_64 yet -- this means if IR used PATCHABLE_RET directly instead of a normal ret, instruction lowering for that platform might do the wrong thing. We think this should be handled at instruction selection time to by default be unpacked for platforms where XRay is not availble yet. 2) The generated section for X86 is different from what is described from the white paper for the sole reason that LLVM allows us to do this neatly. We're taking the opportunity to deviate from the white paper from this perspective to allow us to get richer information from the runtime library. Reviewers: sanjoy, eugenis, kcc, pcc, echristo, rnk Subscribers: niravd, majnemer, atrick, rnk, emaste, bmakam, mcrosier, mehdi_amini, llvm-commits Differential Revision: http://reviews.llvm.org/D19904 llvm-svn: 275367
2016-07-11Add a 'Returned' intrinsic property corresponding to the 'returned' argument ↵Hal Finkel3-1/+10
attribute This will be used by the upcoming llvm.noalias intrinsic. Differential Revision: http://reviews.llvm.org/D22201 llvm-svn: 275034
2016-07-08TableGen: Update style in CodeGenIntrinsics. NFCJustin Bogner1-103/+96
Ran clang-format to remove the namespace indentation, and stopped repeating names in doc comments since I was updating every line anyway. llvm-svn: 274919
2016-07-05TableGen: avoid string copy.Tim Northover1-1/+1
llvm-svn: 274584
2016-07-05AArch64: TableGenerate system instruction operands.Tim Northover4-1/+329
The way the named arguments for various system instructions are handled at the moment has a few problems: - Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp - That weird Mapping class that I have no idea what I was on when I thought it was a good idea. - Searches are performed linearly through the entire list. - We print absolutely all registers in upper-case, even though some are canonically mixed case (SPSel for example). - The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated to comments in our implementation, with a slightly opaque hex value indicating the canonical encoding LLVM will use. This adds a new TableGen backend to produce efficiently searchable tables, and switches AArch64 over to using that infrastructure. llvm-svn: 274576
2016-07-05TableGen: promote "code" type from syntactic sugar.Tim Northover1-1/+1
It's being immediately converted to a "string", but being able to tell what type the field was originally can be useful in backends. llvm-svn: 274575
2016-07-04[TableGen] Remove dead code. NFCI.Davide Italiano1-28/+0
llvm-svn: 274515
2016-07-04Add writeonly IR attributeNicolai Haehnle3-1/+20
Summary: This complements the earlier addition of IntrWriteMem and IntrWriteArgMem LLVM intrinsic properties, see D18291. Also start using the attribute for memset, memcpy, and memmove intrinsics, and remove their special-casing in BasicAliasAnalysis. Reviewers: reames, joker.eph Subscribers: joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D18714 llvm-svn: 274485
2016-06-24Revert "Revert "[misched] Extend scheduler to handle unsupported features""Simon Dardis2-1/+37
This reverts commit r273565. This was an over-eager revert. llvm-svn: 273658
2016-06-23[TableGen] Use StringRef::compare instead of != and <. NFC.Ahmed Bougacha1-2/+2
The previous code would always do 1 or 2 prefix compares; explicitly only do one. This speeds up debug -gen-asm-matcher by ~10% (e.g. X86: 40s -> 35s). llvm-svn: 273583
2016-06-23Revert "[misched] Extend scheduler to handle unsupported features"Simon Dardis2-37/+1
This reverts commit r273551. Patch contained a wrong check for isUnsupported. llvm-svn: 273565
2016-06-23[misched] Extend scheduler to handle unsupported featuresSimon Dardis2-1/+37
Currently isComplete = 1 requires that every instruction must be described, declared unsupported or marked as having no scheduling information for a processor. For some backends such as MIPS, this requirement entails long regex lists of instructions that are unsupported. This patch teaches Tablegen to skip over instructions that are associated with unsupported feature when checking if the scheduling model is complete. Patch by: Daniel Sanders Contributions by: Simon Dardis Reviewers: MatzeB Differential Reviewer: http://reviews.llvm.org/D20522 llvm-svn: 273551
2016-06-21TableGen/CodeGenSchedule: Move some getAllDerivedDefinitions() calls out of ↵Matthias Braun2-3/+11
inner loops This cuts the runtime of the two slowest tblgen invocations in aarch64 in half for me... llvm-svn: 273235
2016-06-20test commit: remove trailing whitespaceThomas Jablin1-1/+1
llvm-svn: 273197
2016-06-12Run clang-tidy's performance-unnecessary-copy-initialization over LLVM.Benjamin Kramer2-2/+2
No functionality change intended. llvm-svn: 272516
2016-06-09Search for llvm-symbolizer binary in the same directory as argv[0], beforeRichard Smith1-1/+1
looking for it along $PATH. This allows installs of LLVM tools outside of $PATH to find the symbolizer and produce pretty backtraces if they crash. llvm-svn: 272232
2016-06-08Apply most suggestions of clang-tidy's performance-unnecessary-value-paramBenjamin Kramer4-16/+13
Avoids unnecessary copies. All changes audited & pass tests with asan. No functional change intended. llvm-svn: 272190
2016-06-03AsmWriterEmitter.cpp assumes that all operands of a printed aliasSjoerd Meijer1-3/+4
will appear after a blank. This assumption does not hold in the ARM target. Patch by: Roger Ferrer Ibanez Differential Revision: http://reviews.llvm.org/D20234 llvm-svn: 271666
2016-06-03Currently AsmWriterEmiter.cpp (used by tblgen -gen-asm-writer) does notSjoerd Meijer1-2/+34
consider the Predicates attached to InstAlias when generating printAliasInstr. This forces users of printAliasInstr to check those predicates beforehand. This commit adds them in the condition set of the IAPrinter object. Patch by: Roger Ferrer Ibanez Differential Revision: http://reviews.llvm.org/D20233 llvm-svn: 271665
2016-05-27Apply clang-tidy's misc-move-constructor-init throughout LLVM.Benjamin Kramer4-16/+18
No functionality change intended, maybe a tiny performance improvement. llvm-svn: 270997
2016-05-27Avoid some copies by using const references.Benjamin Kramer1-1/+1
clang-tidy's performance-unnecessary-copy-initialization with some manual fixes. No functional changes intended. llvm-svn: 270988
2016-05-25TableGen: Use StringRef instead of std::stringMatt Arsenault2-4/+4
llvm-svn: 270741
2016-05-17Fix Clang-tidy modernize-use-bool-literals in generated Target code; other ↵Eugene Zelenko2-51/+80
minor fixes; other minor fixes. Make generated code more readable. Fix some Include What You Use warnings. Differential revision: http://reviews.llvm.org/D20317 llvm-svn: 269783
2016-05-10SDAG: Make SelectCodeCommon return voidJustin Bogner1-2/+3
This means SelectCode unconditionally returns nullptr now. I'll follow up with a change to make that return void as well, but it seems best to keep that one very mechanical. This is part of the work to have Select return void instead of an SDNode *, which is in turn part of llvm.org/pr26808. llvm-svn: 269136
2016-05-06[TableGen] AsmMatcher: support for default values for optional operandsSam Kolton1-31/+117
Summary: This change allows to specify "DefaultMethod" for optional operand (IsOptional = 1) in AsmOperandClass that return default value for operand. This is used in convertToMCInst to set default values in MCInst. Previously if you wanted to set default value for operand you had to create custom converter method. With this change it is possible to use standard converters even when optional operands presented. Reviewers: tstellarAMD, ab, craig.topper Subscribers: jyknight, dsanders, arsenm, nhaustov, llvm-commits Differential Revision: http://reviews.llvm.org/D18242 llvm-svn: 268726
2016-05-06[TableGen] Fix a memory leak when creating SwitchOpcodeMatchers.Craig Topper1-1/+2
llvm-svn: 268712
2016-05-06[TableGen] Remove isSafeToReorderWithPatternPredicate from DAGISelMatchers ↵Craig Topper1-49/+0
as its not used anymore. llvm-svn: 268711
2016-05-06[TableGen] Remove getHash support from DAGISelMatcher. It hasn't been used ↵Craig Topper2-95/+0
for some time. llvm-svn: 268706
2016-05-06[TableGen] Remove SinkPatternPredicates from the DAG isel matcher optimizer.Craig Topper1-54/+0
Pattern predicates already appear to be emitted as far down as they can be. The optimization was making no changes on any in-tree target. llvm-svn: 268705
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