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2020-03-02Explicitly include <cassert> when using assertJoerg Sonnenberger2-0/+2
Depending on the OS used, a module-enabled build can fail due to the special handling <cassert> gets as textual header.
2020-02-29Avoid including FileSystem.h from MemoryBuffer.hReid Kleckner2-0/+2
Lots of headers pass around MemoryBuffer objects, but very few open them. Let those that do include FileSystem.h. Saves ~250 includes of Chrono.h & FileSystem.h: $ diff -u thedeps-before.txt thedeps-after.txt | grep '^[-+] ' | sort | uniq -c | sort -nr 254 - ../llvm/include/llvm/Support/FileSystem.h 253 - ../llvm/include/llvm/Support/Chrono.h 237 - ../llvm/include/llvm/Support/NativeFormatting.h 237 - ../llvm/include/llvm/Support/FormatProviders.h 192 - ../llvm/include/llvm/ADT/StringSwitch.h 190 - ../llvm/include/llvm/Support/FormatVariadicDetails.h ... This requires duplicating the file_t typedef, which is unfortunate. I sunk the choice of mapping mode down into the cpp file using variable template specializations instead of class members in headers.
2020-02-25Fix DfaEmitter::visitDfaState() crash in MSVC x86 debug builds (PR44945)Hans Wennborg2-5/+8
No functionality change (intended), but this seems to make the code a bit clearer for the compiler and maybe for human readers too.
2020-02-24[MC] Widen the functional unit type from 32 to 64 bits.Bevin Hansson1-2/+2
Summary: The type used to represent functional units in MC is 'unsigned', which is 32 bits wide. This is currently not a problem in any upstream target as no one seems to have hit the limit on this yet, but in our downstream one, we need to define more than 32 functional units. Increasing the size does not seem to cause a huge size increase in the binary (an llc debug build went from 1366497672 to 1366523984, a difference of 26k), so perhaps it would be acceptable to have this patch applied upstream as well. Subscribers: hiraditya, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71210
2020-02-21[X86] Add a new format type for instructions that represent named prefix ↵Craig Topper2-0/+4
bytes like data16 and rep. Use it to make a simpler version of isPrefix. isPrefix was added to support the patches to align branches. it relies on a switch over instruction names. This moves those opcodes to a new format so the information is tablegen and we can just check for a specific value in some bits in TSFlags instead. I've left the other function in place for now so that the existing patches in phabricator will still work. I'll work with the owner to get them migrated.
2020-02-19TableGen: Fix logic for default operandsMatt Arsenault1-5/+9
This was checking for default operands in the current DAG instruction, rather than the correct result operand list. I'm not entirly sure how this managed to work before, but was failing for me when multiple default operands were overridden.
2020-02-19Add <128 x i1> as an intrinsic typeKrzysztof Parzyszek1-1/+3
2020-02-19[TableGen] Diagnose undefined fields when generating searchable tablesJay Foad1-1/+1
Summary: Previously TableGen would crash trying to print the undefined value as an integer. Change-Id: I3900071ceaa07c26acafb33bc49966d7d7a02828 Reviewers: nhaehnle Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74210
2020-02-18[TBLGEN] Emit register pressure set enumStanislav Mekhanoshin2-1/+15
Differential Revision: https://reviews.llvm.org/D74649
2020-02-18Drop a constexpr in favor of const, MSVC complains.Benjamin Kramer1-1/+1
lib\Target\Hexagon\HexagonGenDFAPacketizer.inc(109): error C2131: expression did not evaluate to a constant
2020-02-18Move DFA tables into the read-only data segmant.Benjamin Kramer2-5/+6
2020-02-17[TBLGEN] Inhibit generation of unneeded psetsStanislav Mekhanoshin2-1/+7
Differential Revision: https://reviews.llvm.org/D74744
2020-02-17[TableGen] Don't elide bitconverts in PatFrag fragments.Simon Tatham1-0/+7
Summary: In the DAG pattern backend, `SimplifyTree` simplifies a pattern by removing bitconverts between two identical types. But that function is also run on the fragments list in instances of `PatFrags`, in which the types haven't been specified yet. So the input and output of the bitconvert always evaluate to the empty set of types, which makes them compare equal. So the test always passes, and bitconverts are unconditionally removed from the PatFrag RHS. Fixed by spotting the empty type set and using it to inhibit the optimization. Reviewers: nhaehnle, hfinkel Reviewed By: nhaehnle Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74627
2020-02-14[TBLGEN] Allow to override RC weightStanislav Mekhanoshin3-3/+16
Differential Revision: https://reviews.llvm.org/D74509
2020-02-12[TBLGEN] Fix subreg value overflow in DAGISelMatcherStanislav Mekhanoshin5-3/+25
Tablegen's DAGISelMatcher emits integers in a VBR format, so if an integer is below 128 it can fit into a single byte, otherwise high bit is set, next byte is used etc. MatcherTable is essentially an unsigned char table. When SelectionDAGISel parses the table it does a reverse translation. In a situation when numeric value of an integer to emit is unknown it can be emitted not as OPC_EmitInteger but as OPC_EmitStringInteger using a symbolic name of the value. In this situation the value should not exceed 127. One of the situations when OPC_EmitStringInteger is used is if we need to emit a subreg into a matcher table. However, number of subregs can exceed 127. Currently last defined subreg for AMDGPU is 192. That results in a silent bug in the ISel with matcher reading from an invalid offset. Fixed this bug to emit actual VBR encoded value for a subregs which value exceeds 127. Differential Revision: https://reviews.llvm.org/D74368
2020-02-10Revert "Remove redundant "std::move"s in return statements"Bill Wendling1-20/+20
The build failed with error: call to deleted constructor of 'llvm::Error' errors. This reverts commit 1c2241a7936bf85aa68aef94bd40c3ba77d8ddf2.
2020-02-10Remove redundant "std::move"s in return statementsBill Wendling1-20/+20
2020-02-02[NFC] Refactor TableGen for attributesTyker1-89/+23
Summary: this patch makes tablegen generate llvm attributes in a more generic and simpler (at least to me). changes: make tablegen generate ... ATTRIBUTE_ENUM(Alignment,align) ATTRIBUTE_ENUM(AllocSize,allocsize) ... which can be used to generate most of what was previously used and more. Tablegen was also generating attributes from 2 identical files leading to identical output. so I removed one of them and made user use the other. Reviewers: jdoerfert, thakis, aaron.ballman Reviewed By: aaron.ballman Subscribers: mgorny, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72455
2020-02-02Revert "[NFC] Refactor TableGen for attributes"Tyker1-23/+89
This reverts commit 4dba14cf37abda16ab33cb748a5c762dae2e95e9.
2020-02-02[NFC] Refactor TableGen for attributesTyker1-89/+23
Summary: this patch makes tablegen generate llvm attributes in a more generic and simpler (at least to me). changes: make tablegen generate ... ATTRIBUTE_ENUM(Alignment,align) ATTRIBUTE_ENUM(AllocSize,allocsize) ... which can be used to generate most of what was previously used and more. Tablegen was also generating attributes from 2 identical files leading to identical output. so I removed one of them and made user use the other. Reviewers: jdoerfert, thakis, aaron.ballman Reviewed By: aaron.ballman Subscribers: mgorny, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72455
2020-01-29Address implicit conversions detected by g++ 5 only.Benjamin Kramer1-2/+2
2020-01-29Fix a couple more implicit conversions that Clang doesn't diagnose.Benjamin Kramer1-1/+2
2020-01-28Make llvm::StringRef to std::string conversions explicit.Benjamin Kramer31-191/+206
This is how it should've been and brings it more in line with std::string_view. There should be no functional change here. This is mostly mechanical from a custom clang-tidy check, with a lot of manual fixups. It uncovers a lot of minor inefficiencies. This doesn't actually modify StringRef yet, I'll do that in a follow-up.
2020-01-27TableGen: Try to fix expensive checks failuresMatt Arsenault1-1/+1
2020-01-27[tablegen] Emit string literals instead of char arraysLuke Drummond5-28/+102
This changes the generated (Instr|Asm|Reg|Regclass)Name tables from this form: extern const char HexagonInstrNameData[] = { /* 0 */ 'G', '_', 'F', 'L', 'O', 'G', '1', '0', 0, /* 9 */ 'E', 'N', 'D', 'L', 'O', 'O', 'P', '0', 0, /* 18 */ 'V', '6', '_', 'v', 'd', 'd', '0', 0, /* 26 */ 'P', 'S', '_', 'v', 'd', 'd', '0', 0, [...] }; ...to this: extern const char HexagonInstrNameData[] = { /* 0 */ "G_FLOG10\0" /* 9 */ "ENDLOOP0\0" /* 18 */ "V6_vdd0\0" /* 26 */ "PS_vdd0\0" [...] }; This should make debugging and exploration a lot easier for mortals, while providing a significant compile-time reduction for common compilers. To avoid issues with low implementation limits, this is disabled by default for visual studio. To force output one way or the other, pass `--long-string-literals=<bool>` to `tablegen` Reviewers: mstorsjo, rnk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D73044 A variation of this patch was originally committed in ce23515f5ab011 and then reverted in e464b31c due to build failures.
2020-01-24TableGen/GlobalISel: Handle non-leaf EXTRACT_SUBREGMatt Arsenault1-44/+85
This previously only handled EXTRACT_SUBREGs from leafs, such as operands directly in the original output. Handle extracting from a result instruction.
2020-01-24TableGen: Work around assert on Mips register definitionsMatt Arsenault1-2/+8
This would hit the "Biggest class wasn't first" assert in getMatchingSubClassWithSubRegs in a future patch for EXTRACT_SUBREG handling. Mips defines 4 identical register classes (MSA128B, MSA128H, MSA128BW, MSA128D). These have the same set of registers, and only differ by the isel type. I believe this is an ill formed way of defining registers, that probably is just to work around the inconvenience of mixing different types in a single register class in DAG patterns. Since these all have the same size, they would all sort to the beginning, but you would not necessarily get the same super register at the front as the assert enforces. Breaking the ambiguity by also sorting by name doesn't work, since each of these register classes all want to be first. Force sorting of the original register class if the size is the same.
2020-01-23Revert "[tablegen] Emit string literals instead of char arrays"Sergej Jaskiewicz5-85/+18
This reverts commit ce23515f5ab01161c98449d833b3ae013b553aa8. That commit broke some builds on Windows: http://lab.llvm.org:8011/builders/clang-x64-windows-msvc/builds/13870
2020-01-23[tablegen] Emit string literals instead of char arraysLuke Drummond5-18/+85
This changes the generated (Instr|Asm|Reg|Regclass)Name tables from this form: extern const char HexagonInstrNameData[] = { /* 0 */ 'G', '_', 'F', 'L', 'O', 'G', '1', '0', 0, /* 9 */ 'E', 'N', 'D', 'L', 'O', 'O', 'P', '0', 0, /* 18 */ 'V', '6', '_', 'v', 'd', 'd', '0', 0, /* 26 */ 'P', 'S', '_', 'v', 'd', 'd', '0', 0, [...] }; ...to this: extern const char HexagonInstrNameData[] = { /* 0 */ "G_FLOG10\0" /* 9 */ "ENDLOOP0\0" /* 18 */ "V6_vdd0\0" /* 26 */ "PS_vdd0\0" [...] }; This should make debugging and exploration a lot easier for mortals, while providing a significant compile-time reduction for common compilers. To avoid issues with low implementation limits, this is disabled by default for visual studio or when cross-compiling. To force output one way or the other, pass `--long-string-literals=<bool>` to `tablegen` Reviewers: mstorsjo, rnk Subscribers: llvm-commit Differential Revision: https://reviews.llvm.org/D73044
2020-01-17Revert "Avoid creating an immutable map in the Automaton class."Dmitri Gribenko1-2/+8
This reverts commit 051d330314cb1f175025ca37da8e5e1d851e1790. It broke buildbots, for example, http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/21908.
2020-01-16Avoid creating an immutable map in the Automaton class.Marcello Maggioni1-8/+2
Summary: In the DFAPacketizer we copy the Transitions array into a map in order to later access the transitions based on a "Current State/Action" pair as a key. This map lives in the Automaton object used by the DFAPacketizer. It is never changed during the life of the object after having been created during the creation of the Automaton itself. This map creation can make the creation of a DFAPacketizer quite expensive if the target contains a considerable amount of transition states. Considering that TableGen already generates a sorted list of transitions by State/Action pairs we could just use that directly in our Automaton and search entries with std::lower_bound instead of copying it in a map and paying the execution time and memory cost. Reviewers: jmolloy, ThomasRaoux Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72682
2020-01-16TableGen/GlobalISel: Fix srcvalue inputsMatt Arsenault1-0/+4
Allow using srcvalue for discarding pattern inputs.
2020-01-15TableGen: Delete some copy constuctorsMatt Arsenault2-3/+6
Some register related machinery relies on uniqued, static pointers for register classes and subregisters, so try to make sure these are never copied.
2020-01-15TableGen/GlobalISel: Don't take reference to temporary valuesMatt Arsenault1-3/+3
These return temporary Optional<> values which are immediately destroyed. I'm not sure why no sanitizers seem to have caught this, but I encountered crashes on these in a future patch.
2020-01-15TableGen/GlobalISel: Don't reconstruct CodeGenRegBankMatt Arsenault1-2/+2
The maps for dealing with the relationships between different register classes and subregister indexes rely on unique pointers for every class/index. By constructing a second copy of CodeGenRegBank, two different pointer values existed for a given subregister depending on where you were querying. Use the existing CodeGenRegBank owned by the CodeGenTarget instead of constructing a second copy. This avoids incorrectly failing map lookups in a future change.
2020-01-11[X86][Disassembler] Shrink X86GenDisassemblerTables.inc from 36M to 6.1MFangrui Song1-46/+42
In x86Disassembler{OneByte,TwoByte,...}Codes, "/* EmptyTable */" is very common. Omitting it saves lots of space. Also, there is no need to display a table entry in multiple lines. It is also common that the whole OpcodeDecision is { MODRM_ONEENTRY, 0}. Make use of zero-initialization.
2020-01-10[AArch64] Add isAuthenticated predicate to MCInstDescVedant Kumar4-0/+4
Add a predicate to MCInstDesc that allows tools to determine whether an instruction authenticates a pointer. This can be used by diagnostic tools to hint at pointer authentication failures. Differential Revision: https://reviews.llvm.org/D70329 rdar://55089604
2020-01-09TableGen/GlobalISel: Fix pattern matching of immarg literalsMatt Arsenault5-26/+65
For arguments that are not expected to be materialized with G_CONSTANT, this was emitting predicates which could never match. It was first adding a meaningless LLT check, which would always fail due to the operand not being a register. Infer the cases where a literal should check for an immediate operand, instead of a register This avoids needing to invent a special way of representing timm literal values. Also handle immediate arguments in GIM_CheckLiteralInt. The comments stated it handled isImm() and isCImm(), but that wasn't really true. This unblocks work on the selection of all of the complicated AMDGPU intrinsics in future commits.
2020-01-09TableGen/GlobalISel: Add way for SDNodeXForm to work on timmMatt Arsenault1-4/+47
The current implementation assumes there is an instruction associated with the transform, but this is not the case for timm/TargetConstant/immarg values. These transforms should directly operate on a specific MachineOperand in the source instruction. TableGen would assert if you attempted to define an equivalent GISDNodeXFormEquiv using timm when it failed to find the instruction matcher. Specially recognize SDNodeXForms on timm, and pass the operand index to the render function. Ideally this would be a separate render function type that looks like void renderFoo(MachineInstrBuilder, const MachineOperand&), but this proved to be somewhat mechanically painful. Add an optional operand index which will only be passed if the transform should only look at the one source operand. Theoretically it would also be possible to only ever pass the MachineOperand, and the existing renderers would check the parent. I think that would be somewhat ugly for the standard usage which may want to inspect other operands, and I also think MachineOperand should eventually not carry a pointer to the parent instruction. Use it in one sample pattern. This isn't a great example, since the transform exists to satisfy DAG type constraints. This could also be avoided by just changing the MachineInstr's arbitrary choice of operand type from i16 to i32. Other patterns have nontrivial uses, but this serves as the simplest example. One flaw this still has is if you try to use an SDNodeXForm defined for imm, but the source pattern uses timm, you still see the "Failed to lookup instruction" assert. However, there is now a way to avoid it.
2020-01-09TableGen/GlobalISel: Address fixmeMatt Arsenault1-5/+9
Don't call computeAvailableFunctionFeatures for every instruction.
2020-01-09[ms] [X86] Use "P" modifier on all branch-target operands in inline X86 ↵Eric Astor2-41/+46
assembly. Summary: Extend D71677 to apply to all branch-target operands, rather than special-casing call instructions. Also add a regression test for llvm.org/PR44272, since this finishes fixing it. Reviewers: thakis, rnk Reviewed By: thakis Subscribers: merge_guards_bot, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D72417
2020-01-09TableGen: Remove unused codeMatt Arsenault1-6/+0
2020-01-09TableGen/GlobalISel: Fix slightly wrong generated commentMatt Arsenault1-1/+1
2020-01-07Fix warnings as errors that occur on sanitizer-x86_64-linuxDaniel Sanders1-4/+4
2020-01-07Remove extraneous semicolon.Bill Wendling1-1/+1
2020-01-07[gicombiner] Add GIMatchTree and use it for the code generationDaniel Sanders11-8/+1769
Summary: GIMatchTree's job is to build a decision tree by zipping all the GIMatchDag's together. Each DAG is added to the tree builder as a leaf and partitioners are used to subdivide each node until there are no more partitioners to apply. At this point, the code generator is responsible for testing any untested predicates and following any unvisited traversals (there shouldn't be any of the latter as the getVRegDef partitioner handles them all). Note that the leaves don't always fit into partitions cleanly and the partitions may overlap as a result. This is resolved by cloning the leaf into every partition it belongs to. One example of this is a rule that can match one of N opcodes. The leaf for this rule would end up in N partitions when processed by the opcode partitioner. A similar example is the getVRegDef partitioner where having rules (add $a, $b), and (add ($a, $b), $c) will result in the former being in the partition for successfully following the vreg-def and failing to do so as it doesn't care which happens. Depends on D69151 Fixed the issues with the windows bots which were caused by stdout/stderr interleaving. Reviewers: bogner, volkan Reviewed By: volkan Subscribers: lkail, mgorny, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69152
2020-01-06[MC] Add parameter `Address` to MCInstrPrinter::printInstructionFangrui Song1-7/+8
Follow-up of D72172. Reviewed By: jhenderson, rnk Differential Revision: https://reviews.llvm.org/D72180
2020-01-06TableGen/GlobalISel: Handle default operands that are usedMatt Arsenault1-7/+37
Copy the logic from the existing handling in the DAG matcher emittter. This will enable some AMDGPU pattern cleanups without breaking GlobalISel tests, and eventually handle importing more patterns. The test is a bit annoying since the sections seem to randomly sort themselves if anything else is added in the future.
2020-01-06[NFC] Fix trivial typos in commentsJames Henderson2-4/+4
Reviewed By: jhenderson Differential Revision: https://reviews.llvm.org/D72143 Patch by Kazuaki Ishizaki.
2020-01-03Revert "[gicombiner] Add GIMatchTree and use it for the code generation"Daniel Sanders11-1769/+8
All the windows bots are failing match-tree.td and there's no obvious cause that I can see. It's not just the %p formatting problem. My best guess is that there's an ordering issue too but I'll need further information to figure that out. Revert while I'm investigating. This reverts commit 64f1bb5cd2c6d69af7c74ec68840029603560238 and 77d4b5f5feff663e70b347516cc4c77fa5cd2a20
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