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path: root/llvm/utils/TableGen/IntrinsicEmitter.cpp
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2022-06-01[ValueTypes] Define MVTs for v128i2/v64i4 as well as i2 and i4.Hendrik Greving1-19/+25
Adds MVT::v128i2, MVT::v64i4, and implied MVT::i2, MVT::i4. Keeps MVT::i2, MVT::i4 lowering actions as `expand`, which should be removed once targets set this explicitly. Adjusts 11 lit tests to reflect slightly different behavior during DAG combine. Differential Revision: https://reviews.llvm.org/D125247
2022-03-25Reapply "[Intrinsics] Add `nocallback` to the default intrinsic attributes"Johannes Doerfert1-4/+9
This reverts commit c5f789050daab25aad6770790987e2b7c0395936 and reapplies 7aea3ea8c3b33c9bb338d5d6c0e4832be1d09ac3 with additional test changes.
2022-03-24Revert "[Intrinsics] Add `nocallback` to the default intrinsic attributes"Johannes Doerfert1-9/+4
This reverts commit 7aea3ea8c3b33c9bb338d5d6c0e4832be1d09ac3 as it breaks the buildbots. I didn't see these failures in the pre-merge checks, looking into it.
2022-03-24[Intrinsics] Add `nocallback` to the default intrinsic attributesJohannes Doerfert1-4/+9
Most intrinsics, especially "default" ones, will not call back into the IR module. `nocallback` encodes this nicely. As it was not used before, this patch also makes use of `nocallback` in the Attributor which results in many more `norecurse` deductions. Tablegen part is mechanical, test updates by script. Differential Revision: https://reviews.llvm.org/D118680
2022-03-22[VP] Preserve address space of pointer for strided load/store intrinsics.Craig Topper1-1/+12
This adds LLVMAnyPointerToElt to use instead of LLVMPointerToElt. This allows us to preserve the address space as part of the type overload for the intrinsic, but still require the vector element type to match the pointer type. Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D122042
2022-01-31Cleanup llvm/utils/TableGen headersserge-sans-paille1-1/+0
Based on the output of include-what-you-use. It's an utility directory, so no much impact on other code areas. clang++ -E -Iinclude -I../llvm/include ../llvm/utils/TableGen/*.cpp -std=c++14 -fno-rtti -fno-exceptions | wc -l before: 4327274 after: 4316190 Related discourse thread: https://llvm.discourse.group/t/include-what-you-use-include-cleanup Differential Revision: https://reviews.llvm.org/D118466
2021-12-06[WebAssembly] Implementation of intrinsic for ref.null and HeapType removalPaulo Matos1-0/+6
This patch implements the intrinsic for ref.null. In the process of implementing int_wasm_ref_null_func() and int_wasm_ref_null_extern() intrinsics, it removes the redundant HeapType. This also causes the textual assembler syntax for ref.null to change. Instead of receiving an argument: `func` or `extern`, the instruction mnemonic is either ref.null_func or ref.null_extern, without the need for a further operand. Reviewed By: tlively Differential Revision: https://reviews.llvm.org/D114979
2021-12-04[IR,TableGen] Add support for vec3 intrinsic argumentsJay Foad1-1/+3
Add generic support for vec3 types, and in particular define llvm_v3f32_ty which will be used by AMDGPU's llvm.amdgcn.image.bvh.intersect.ray intrinsic. Differential Revision: https://reviews.llvm.org/D114956
2021-11-03[PowerPC] Implement longdouble pack/unpack builtinsQiu Chaofan1-1/+3
Implement two builtins to pack/unpack IBM extended long double float, according to GCC 'Basic PowerPC Builtin Functions Available ISA 2.05'. Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D112055
2021-05-12[ValueTypes] Rename MVT::getVectorNumElements() to ↵Craig Topper1-1/+1
MVT::getVectorMinNumElements(). Fix some misuses of getVectorNumElements() getVectorNumElements() returns a value for scalable vectors without any warning so it is effectively getVectorMinNumElements(). By renaming it and making getVectorNumElements() forward to it, we can insert a check for scalable vectors into getVectorNumElements() similar to EVT. I didn't do that in this patch because there are still more fixes needed, but I was able to temporarily do it and passed the RISCV lit tests with these changes. The changes to isPow2VectorType and getPow2VectorType are copied from EVT. The change to TypeInfer::EnforceSameNumElts reduces the size of AArch64's isel table. We're now considering SameNumElts to require the scalable property to match which removes some unneeded type checks. This was motivated by the bug I fixed yesterday in 80b9510806cf11c57f2dd87191d3989fc45defa8 Reviewed By: frasercrmck, sdesmalen Differential Revision: https://reviews.llvm.org/D102262
2021-05-07[TableGen] Use range-based for loops (NFC)Coelacanthus1-43/+42
Use range-based for loops in TableGen. Reviewed By: Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D101994
2021-03-02[TableGen] Add IntrNoMerge as intrinsic propertyKrzysztof Parzyszek1-1/+7
There is a function attribute 'nomerge' in addition to 'noduplicate' and 'convergent'. Both 'noduplicate' and 'convergent' have corresponding intrinsic properties. This patch adds an intrinsic property for the 'nomerge' attribute. Differential Revision: https://reviews.llvm.org/D96364
2021-02-07[TableGen] Use ListSeparator (NFC)Kazu Hirata1-77/+31
2021-02-06[TableGen] Use ListSeparator (NFC)Kazu Hirata1-44/+13
2021-01-27IntrinsicEmitter: Change IntrinsicsToAttributesMap from uint8_t[] to uint16_t[]Fangrui Song1-2/+2
We need at least 252 UniqAttributes now, which will soon overflow. Actually with downstream backends we can easily use up the last few values. So bump to uint16_t.
2020-12-30[X86] Add x86_amx type for intel AMX.Luo, Yuanke1-1/+3
The x86_amx is used for AMX intrisics. <256 x i32> is bitcast to x86_amx when it is used by AMX intrinsics, and x86_amx is bitcast to <256 x i32> when it is used by load/store instruction. So amx intrinsics only operate on type x86_amx. It can help to separate amx intrinsics from llvm IR instructions (+-*/). Thank Craig for the idea. This patch depend on https://reviews.llvm.org/D87981. Differential Revision: https://reviews.llvm.org/D91927
2020-10-19[SVE] Replace TypeSize comparison operators in llvm/utils/TableGenDavid Sherwood1-1/+1
In CodeGenDAGPatterns.cpp we were relying upon TypeSize comparison operators for ordering types, when we can actually just use the known minimum size since the scalable property is already being taken into account. Also, in TypeInfer::EnforceSameSize I fixed some implicit TypeSize->uint64_t casts by changing the code to test the equality of TypeSize objects instead. In other places I have replaced calls to getSizeInBits() with getFixedSizeInBits() because we are only ever expecting integer values. Differential Revision: https://reviews.llvm.org/D88947
2020-10-13[PowerPC] Add assemble disassemble intrinsics for MMAAhsan Saghir1-1/+3
This patch adds support for assemble disassemble intrinsics for MMA. Reviewed By: bsaleil, #powerpc Differential Revision: https://reviews.llvm.org/D88739
2020-09-30[X86] Support Intel Key LockerXiang1 Zhang1-1/+3
Key Locker provides a mechanism to encrypt and decrypt data with an AES key without having access to the raw key value by converting AES keys into “handles”. These handles can be used to perform the same encryption and decryption operations as the original AES keys, but they only work on the current system and only until they are revoked. If software revokes Key Locker handles (e.g., on a reboot), then any previous handles can no longer be used. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D88398
2020-08-27[IR] Add NoUndef attribute to Intrinsics.tdJuneyoung Lee1-0/+6
This patch adds NoUndef to Intrinsics.td. The attribute is attached to llvm.assume's operand, because llvm.assume(undef) is UB. It is attached to pointer operands of several memory accessing intrinsics as well. This change makes ValueTracking::getGuaranteedNonPoisonOps' intrinsic check unnecessary, so it is removed. Reviewed By: jdoerfert Differential Revision: https://reviews.llvm.org/D86576
2020-06-30[IR] NoFree IntrinsicProperty.sstefan11-4/+14
Summary: Separate introduction of IntrNoFree property as suggested in D70365 Reviewers: arsenm, nhaehnle Tags: #llvm Differential Revision: https://reviews.llvm.org/D82587
2020-05-27Enable `align <n>` to be used in the intrinsic definition.Michael Liao1-1/+29
- This allow us to specify the (minimal) alignment on an intrinsic's arguments and, more importantly, the return value. Differential Revision: https://reviews.llvm.org/D80422
2020-05-27Refactor argument attribute specification in intrinsic definition. NFC.Michael Liao1-4/+3
- Argument attribute needs specifiying through `ArgIndex<n>` (corresponding to `FirstArgIndex`) to distinguish explicitly from the index number from the overloaded type list. - In addition, `RetIndex` (corresponding to `ReturnIndex`) and `FuncIndex` (corresponding to `FunctionIndex`) are introduced for us to associate attributes on the return value and potentially function itself. Differential Revision: https://reviews.llvm.org/D80422
2020-05-27[IR][BFloat] add BFloat IR intrinsics supportTies Stuij1-1/+3
Summary: This patch is part of a series that adds support for the Bfloat16 extension of the Armv8.6-a architecture, as detailed here: https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a The bfloat type, and its properties are specified in the Arm Architecture Reference Manual: https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile Reviewers: scanon, fpetrogalli, sdesmalen, craig.topper, LukeGeeson Reviewed By: fpetrogalli Subscribers: LukeGeeson, pbarrio, kristof.beyls, hiraditya, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D79707
2020-03-19[VP,Integer,#1] Vector-predicated integer intrinsicsSimon Moll1-2/+11
Summary: This patch adds IR intrinsics for vector-predicated integer arithmetic. It is subpatch #1 of the [integer slice](https://reviews.llvm.org/D57504#1732277) of [LLVM-VP](https://reviews.llvm.org/D57504). LLVM-VP is a larger effort to bring native vector predication to LLVM. Reviewed By: andrew.w.kaylor Differential Revision: https://reviews.llvm.org/D69891
2020-02-19Add <128 x i1> as an intrinsic typeKrzysztof Parzyszek1-1/+3
2019-12-27[Intrinsic] Delete tablegen rules of llvm.{sig,}{setjmp,longjmp}Fangrui Song1-28/+0
2019-12-11[IR] Split out target specific intrinsic enums into separate headersReid Kleckner1-11/+65
This has two main effects: - Optimizes debug info size by saving 221.86 MB of obj file size in a Windows optimized+debug build of 'all'. This is 3.03% of 7,332.7MB of object file size. - Incremental step towards decoupling target intrinsics. The enums are still compact, so adding and removing a single target-specific intrinsic will trigger a rebuild of all of LLVM. Assigning distinct target id spaces is potential future work. Part of PR34259 Reviewers: efriedma, echristo, MaskRay Reviewed By: echristo, MaskRay Differential Revision: https://reviews.llvm.org/D71320
2019-12-11[TableGen] Remove unused target intrinsic generation logicReid Kleckner1-40/+12
AMDGPU was the last in tree target to use this tablegen mode. I plan to split up the global intrinsic enum similar to the way that clang diagnostics are split up today. I don't plan to build on this mode. Reviewers: arsenm, echristo, efriedma Reviewed By: echristo Differential Revision: https://reviews.llvm.org/D71318
2019-10-02[IntrinsicEmitter] Add overloaded type VecOfBitcastsToInt for SVE intrinsicsKerry McLaughlin1-1/+4
Summary: This allows intrinsics such as the following to be defined: - declare <n x 4 x i32> @llvm.something.nxv4f32(<n x 4 x i32>, <n x 4 x i1>, <n x 4 x float>) ...where <n x 4 x i32> is derived from <n x 4 x float>, but the element needs bitcasting to int. Reviewers: c-rhodes, sdesmalen, rovka Reviewed By: c-rhodes Subscribers: tschuett, hiraditya, jdoerfert, llvm-commits, cfe-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68021 llvm-svn: 373437
2019-09-20[IntrinsicEmitter] Add overloaded types for SVE intrinsics (Subdivide2 & ↵Kerry McLaughlin1-1/+7
Subdivide4) Summary: Both match the type of another intrinsic parameter of a vector type, but where each element is subdivided to form a vector with more elements of a smaller type. Subdivide2Argument allows intrinsics such as the following to be defined: - declare <vscale x 4 x i32> @llvm.something.nxv4i32(<vscale x 8 x i16>) Subdivide4Argument allows intrinsics such as: - declare <vscale x 4 x i32> @llvm.something.nxv4i32(<vscale x 16 x i8>) Tests are included in follow up patches which add intrinsics using these types. Reviewers: sdesmalen, SjoerdMeijer, greened, rovka Reviewed By: sdesmalen Subscribers: rovka, tschuett, jdoerfert, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67549 llvm-svn: 372380
2019-08-27[IntrinsicEmitter] Support scalable vectors in intrinsicsCullen Rhodes1-1/+4
Summary: This patch adds support for scalable vectors in intrinsics, enabling intrinsics such as the following to be defined: declare <vscale x 4 x i32> @llvm.something.nxv4i32(<vscale x 4 x i32>) Support for this is implemented by defining a new type descriptor for scalable vectors and adding mangling support for scalable vector types in the name mangling scheme used by 'any' types in intrinsic signatures. Tests have been added for IRBuilder to test scalable vectors work as expected when using intrinsics through this interface. This required implementing an intrinsic that is explicitly defined with scalable vectors, e.g. LLVMType<nxv4i32>, an SVE floating-point convert intrinsic was used for this. The behaviour of the overloaded type LLVMScalarOrSameVectorWidth with scalable vectors is tested using the existing masked load intrinsic. Also added an .ll test to test the Verifier catches a bad intrinsic argument when passing a fixed-width predicate (mask) to the masked.load intrinsic where a scalable is expected. Patch by Paul Walker Reviewed By: sdesmalen Differential Revision: https://reviews.llvm.org/D65930 llvm-svn: 370053
2019-08-18TableGen: Revert changes from r369038Matt Arsenault1-3/+1
These aren't needed for a specific use yet, and I meant to not commit these. llvm-svn: 369201
2019-08-15MVT: Add v3i16/v3f16 vectorsMatt Arsenault1-1/+3
AMDGPU has some buffer intrinsics which theoretically could use this. Some of the generated tables include the 3 and 4 element vector versions of these rounded to 64-bits, which is ambiguous. Add these to help the table disambiguate these. Assertion change is for the path odd sized vectors now take for R600. v3i16 is widened to v4i16, which then needs to be promoted to v4i32. llvm-svn: 369038
2019-08-14[Intrinsics] Add a 'NoAlias' intrinsic property; annotate llvm.memcpyDavid Bolvansky1-0/+6
Reviewers: jdoerfert Reviewed By: jdoerfert Differential Revision: https://reviews.llvm.org/D66158 llvm-svn: 368810
2019-07-17[Attributor] Deduce "willreturn" function attributeHideto Ueno1-2/+12
Summary: Deduce the "willreturn" attribute for functions. For now, intrinsics are not willreturn. More annotation will be done in another patch. Reviewers: jdoerfert Subscribers: jvesely, nhaehnle, nicholas, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63046 llvm-svn: 366335
2019-07-17[TableGen] Do not set ReadNone attribute on intrinsics with side effectsMomchil Velikov1-1/+3
If an intrinsic is defined without outputs, but having side effects, it still can be removed completely from the program. This patch makes TableGen not set Attribute::ReadNone for intrinsics which are declared with IntrHasSideEffects. Differential Revision: https://reviews.llvm.org/D64414 llvm-svn: 366312
2019-06-26Teach TableGen Intrin Emitter to handle LLVMPointerType<llvm_any_ty>Erich Keane1-0/+3
r363233 rewrote a bunch of the Intrin Emitter code, however the new function to update the arg codes did not properly consider a pointer to an any. This patch adds that logic. Differential Revision: https://reviews.llvm.org/D63507 llvm-svn: 364364
2019-06-13Improve reduction intrinsics by overloading result value.Sander de Smalen1-1/+4
This patch uses the mechanism from D62995 to strengthen the definitions of the reduction intrinsics by letting the scalar result/accumulator type be overloaded from the vector element type. For example: ; The LLVM LangRef specifies that the scalar result must equal the ; vector element type, but this is not checked/enforced by LLVM. declare i32 @llvm.experimental.vector.reduce.or.i32.v4i32(<4 x i32> %a) This patch changes that into: declare i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32> %a) Which has the type-constraint more explicit and causes LLVM to check the result type with the vector element type. Reviewers: RKSimon, arsenm, rnk, greened, aemerson Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D62996 llvm-svn: 363240
2019-06-13[IntrinsicEmitter] Extend argument overloading with forward references.Sander de Smalen1-11/+62
Extend the mechanism to overload intrinsic arguments by using either backward or forward references to the overloadable arguments. In for example: def int_something : Intrinsic<[LLVMPointerToElt<0>], [llvm_anyvector_ty], []>; LLVMPointerToElt<0> is a forward reference to the overloadable operand of type 'llvm_anyvector_ty' and would allow intrinsics such as: declare i32* @llvm.something.v4i32(<4 x i32>); declare i64* @llvm.something.v2i64(<2 x i64>); where the result pointer type is deduced from the element type of the first argument. If the returned pointer is not a pointer to the element type, LLVM will give an error: Intrinsic has incorrect return type! i64* (<4 x i32>)* @llvm.something.v4i32 Reviewers: RKSimon, arsenm, rnk, greened Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D62995 llvm-svn: 363233
2019-03-12IR: Add immarg attributeMatt Arsenault1-1/+6
This indicates an intrinsic parameter is required to be a constant, and should not be replaced with a non-constant value. Add the attribute to all AMDGPU and generic intrinsics that comments indicate it should apply to. I scanned other target intrinsics, but I don't see any obvious comments indicating which arguments are intended to be only immediates. This breaks one questionable testcase for the autoupgrade. I'm unclear on whether the autoupgrade is supposed to really handle declarations which were never valid. The verifier fails because the attributes now refer to a parameter past the end of the argument list. llvm-svn: 355981
2019-02-12[tablegen] Add locations to many PrintFatalError() callsDaniel Sanders1-2/+3
Summary: While working on the GISel Combiner, I noticed I was producing location-less error messages fairly often and set about fixing this. In the process, I noticed quite a few places elsewhere in TableGen that also neglected to include a relevant location. This patch adds locations to errors that relate to a specific record (or a field within it) and also have easy access to the relevant location. This is particularly useful when multiclasses are involved as many of these errors refer to the full name of a record and it's difficult to guess which substring is grep-able. Unfortunately, tablegen currently only supports Record granularity so it's not currently possible to point at a specific Init so these sometimes point at the record that caused the error rather than the precise origin of the error. Reviewers: bogner, aditya_nandakumar, volkan, aemerson, paquette, nhaehnle Reviewed By: nhaehnle Subscribers: jdoerfert, nhaehnle, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58077 llvm-svn: 353862
2019-01-23[IR] Match intrinsic parameter by scalar/vectorwidthSimon Pilgrim1-1/+1
This patch replaces the existing LLVMVectorSameWidth matcher with LLVMScalarOrSameVectorWidth. The matching args must be either scalars or vectors with the same number of elements, but in either case the scalar/element type can differ, specified by LLVMScalarOrSameVectorWidth. I've updated the _overflow intrinsics to demonstrate this - allowing it to return a i1 or <N x i1> overflow result, matching the scalar/vectorwidth of the other (add/sub/mul) result type. The masked load/store/gather/scatter intrinsics have also been updated to use this, although as we specify the reference type to be llvm_anyvector_ty we guarantee the mask will be <N x i1> so no change in behaviour Differential Revision: https://reviews.llvm.org/D57090 llvm-svn: 351957
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth1-4/+3
to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
2018-11-14Mark @llvm.trap coldVedant Kumar1-1/+10
A call to @llvm.trap can be expected to be cold (i.e. unlikely to be reached in a normal program execution). Outlining paths which unconditionally trap is an important memory saving. As the hot/cold splitting pass (imho) should not treat all noreturn calls as cold, explicitly mark @llvm.trap cold so that it can be outlined. Split out of https://reviews.llvm.org/D54244. Differential Revision: https://reviews.llvm.org/D54329 llvm-svn: 346885
2018-07-09[Power9] Add __float128 builtins for Round To OddStefan Pintilie1-1/+3
GCC has builtins for these round to odd instructions: __float128 __builtin_sqrtf128_round_to_odd (__float128) __float128 __builtin_{add,sub,mul,div}f128_round_to_odd (__float128, __float128) __float128 __builtin_fmaf128_round_to_odd (__float128, __float128, __float128) Differential Revision: https://reviews.llvm.org/D47550 llvm-svn: 336578
2018-06-23[IR] Split Intrinsics.inc into enums and implementationsReid Kleckner1-21/+29
Implements PR34259 Intrinsics.h is a very popular header. Most LLVM TUs care about things like dbg_value, but they don't care how they are implemented. After I split these out, IntrinsicImpl.inc is 1.7 MB, so this saves each LLVM TU from scanning 1.7 MB of source that gets pre-processed away. It also means we can modify intrinsic properties without triggering a full rebuild, but that's probably less of a win. I think the next best thing to do would be to split out the target intrinsics into their own header. Very, very few TUs care about target-specific intrinsics. It's very hard to split up the target independent intrinsics like llvm.expect, assume, and dbg.value, though. llvm-svn: 335407
2018-04-30NFC - Typo fixes lib/VMCore -> lib/IRGabor Buella1-1/+1
llvm-svn: 331166
2017-12-28Avoid int to string conversion in Twine or raw_ostream contexts.Benjamin Kramer1-1/+1
Some output changes from uppercase hex to lowercase hex, no other functionality change intended. llvm-svn: 321526
2017-12-19Silence a bunch of implicit fallthrough warningsAdrian Prantl1-0/+1
llvm-svn: 321114
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