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path: root/llvm/utils/TableGen/InstrInfoEmitter.cpp
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2016-09-13Revert of r281304 as it is causing build bot failures in hexagonSjoerd Meijer1-1/+0
hwloop regression tests. These tests pass locally; will be investigating where these differences come from. llvm-svn: 281306
2016-09-13This adds a new field isAdd to MCInstrDesc. The ARM and Hexagon instructionSjoerd Meijer1-0/+1
descriptions now tag add instructions, and the Hexagon backend is using this to identify loop induction statements. Patch by Sam Parker and Sjoerd Meijer. Differential Revision: https://reviews.llvm.org/D23601 llvm-svn: 281304
2016-07-14XRay: Add entry and exit sledsDean Michael Berris1-3/+3
Summary: In this patch we implement the following parts of XRay: - Supporting a function attribute named 'function-instrument' which currently only supports 'xray-always'. We should be able to use this attribute for other instrumentation approaches. - Supporting a function attribute named 'xray-instruction-threshold' used to determine whether a function is instrumented with a minimum number of instructions (IR instruction counts). - X86-specific nop sleds as described in the white paper. - A machine function pass that adds the different instrumentation marker instructions at a very late stage. - A way of identifying which return opcode is considered "normal" for each architecture. There are some caveats here: 1) We don't handle PATCHABLE_RET in platforms other than x86_64 yet -- this means if IR used PATCHABLE_RET directly instead of a normal ret, instruction lowering for that platform might do the wrong thing. We think this should be handled at instruction selection time to by default be unpacked for platforms where XRay is not availble yet. 2) The generated section for X86 is different from what is described from the white paper for the sole reason that LLVM allows us to do this neatly. We're taking the opportunity to deviate from the white paper from this perspective to allow us to get richer information from the runtime library. Reviewers: sanjoy, eugenis, kcc, pcc, echristo, rnk Subscribers: niravd, majnemer, atrick, rnk, emaste, bmakam, mcrosier, mehdi_amini, llvm-commits Differential Revision: http://reviews.llvm.org/D19904 llvm-svn: 275367
2016-02-16[TableGen] Use range-based for loop. NFCCraig Topper1-2/+2
llvm-svn: 260928
2016-02-11[TableGen] Don't call emitSourceFileHeader a second time in the middle of ↵Craig Topper1-3/+1
the output file. llvm-svn: 260501
2016-02-11[TableGen] Whitespace cleanup in output file. NFCCraig Topper1-14/+14
llvm-svn: 260500
2016-02-11[TableGen] Simplify code slightly. NFCCraig Topper1-6/+3
llvm-svn: 260499
2016-02-01[TableGen] Store result of getInstructionsByEnumValue in an ArrayRef instead ↵Craig Topper1-6/+6
of accidentally copying to a vector. llvm-svn: 259336
2016-01-17[TableGen] Replace instructions() with getInstructionsByEnumValue(). No need ↵Craig Topper1-2/+2
to make an iterator_range when we already have a function that returns an ArrayRef. NFC llvm-svn: 258019
2015-12-05Replace uint16_t with the MCPhysReg typedef in many places. A lot of ↵Craig Topper1-1/+1
physical register arrays already use this typedef. llvm-svn: 254843
2015-10-01[WinEH] Make FuncletLayout more robust against catchretDavid Majnemer1-3/+3
Catchret transfers control from a catch funclet to an earlier funclet. However, it is not completely clear which funclet the catchret target is part of. Make this clear by stapling the catchret target's funclet membership onto the CATCHRET SDAG node. llvm-svn: 249052
2015-09-10Re-commit r247216: "Fix Clang-tidy misc-use-override warnings, other minor ↵Hans Wennborg1-22/+20
fixes" Except the changes that defined virtual destructors as =default, because that ran into problems with GCC 4.7 and overriding methods that weren't noexcept. llvm-svn: 247298
2015-09-10Revert r247216: "Fix Clang-tidy misc-use-override warnings, other minor fixes"Hans Wennborg1-20/+22
This caused build breakges, e.g. http://lab.llvm.org:8011/builders/clang-x86_64-ubuntu-gdb-75/builds/24926 llvm-svn: 247226
2015-09-10Fix Clang-tidy misc-use-override warnings, other minor fixesHans Wennborg1-22/+20
Patch by Eugene Zelenko! Differential Revision: http://reviews.llvm.org/D12740 llvm-svn: 247216
2015-05-28Add support for the convergent flag at the MC and MachineInstr levels.Owen Anderson1-31/+32
llvm-svn: 238450
2015-05-28Expand the Flags field of MCInstrDesc to 64 bits, while simultaneouslyOwen Anderson1-2/+2
shrinking the Size and NumDefs fields to offset the size growth, and reordering the fields to preserve a good packing. This is necessary in the short term for adding a convergent flag, and simultaneously future-proofs us against more flags being added in the future. llvm-svn: 238445
2015-05-26Use std::bitset for SubtargetFeatures.Michael Kuperstein1-4/+4
Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures. Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. This should now be fixed. llvm-svn: 238192
2015-05-13Reverting r237234, "Use std::bitset for SubtargetFeatures"Michael Kuperstein1-4/+4
The buildbots are still not satisfied. MIPS and ARM are failing (even though at least MIPS was expected to pass). llvm-svn: 237245
2015-05-13Use std::bitset for SubtargetFeaturesMichael Kuperstein1-4/+4
Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first two times this was committed (r229831, r233055), it caused several buildbot failures. At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed. llvm-svn: 237234
2015-05-11Fix tablegen's PrintFatalError function to run registered fileJames Y Knight1-4/+2
cleanups. Also, change code in tablegen which printed a message and then called "exit(1)" to use PrintFatalError, instead. This fixes instances where an empty output file was left behind after a failed tablegen invocation, which would confuse subsequent ninja runs into not attempting to rebuild. Differential Revision: http://reviews.llvm.org/D9608 llvm-svn: 237058
2015-03-24Revert "Use std::bitset for SubtargetFeatures"Michael Kuperstein1-4/+4
This reverts commit r233055. It still causes buildbot failures (gcc running out of memory on several platforms, and a self-host failure on arm), although less than the previous time. llvm-svn: 233068
2015-03-24Use std::bitset for SubtargetFeaturesMichael Kuperstein1-4/+4
Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first time this was committed (r229831), it caused several buildbot failures. At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed. Differential Revision: http://reviews.llvm.org/D8542 llvm-svn: 233055
2015-03-13Use the variable names from the TargetInstrInfo source when weEric Christopher1-5/+7
reference them in the generated files. A few characters aren't huge here and CFSetupOpcode is much more readable than S0. llvm-svn: 232132
2015-03-13Add a return after the llvm namespace code for a little extraEric Christopher1-3/+3
readability in generated files. llvm-svn: 232131
2015-02-26Fix a couple of depedent->dependent typos.Eric Christopher1-1/+1
llvm-svn: 230584
2015-02-19Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.Michael Kuperstein1-4/+4
llvm-svn: 229841
2015-02-19Use std::bitset for SubtargetFeaturesMichael Kuperstein1-4/+4
Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. Differential Revision: http://reviews.llvm.org/D7065 llvm-svn: 229831
2015-01-12Target: Allow target specific operand typesTom Stellard1-1/+1
This adds two new fields to the RegisterOperand TableGen class: string OperandNamespace = "MCOI"; string OperandType = "OPERAND_REGISTER"; These fields can be used to specify a target specific operand type, which will be stored in the OperandType member of the MCOperandInfo object. This can be useful for targets that need to store some extra information about operands that cannot be expressed using the target independent types. For example, in the R600 backend, there are operands which can take either registers or immediates and it is convenient to be able to specify this in the TableGen definitions. llvm-svn: 225661
2014-11-23Tablegen output formatting fixes.Craig Topper1-2/+4
llvm-svn: 222633
2014-08-20Add isInsertSubreg property.Quentin Colombet1-0/+1
This patch adds a new property: isInsertSubreg and the related target hooks: TargetIntrInfo::getInsertSubregInputs and TargetInstrInfo::getInsertSubregLikeInputs to specify that a target specific instruction is a (kind of) INSERT_SUBREG. The approach is similar to r215394. <rdar://problem/12702965> llvm-svn: 216139
2014-08-20Add isExtractSubreg property.Quentin Colombet1-0/+1
This patch adds a new property: isExtractSubreg and the related target hooks: TargetIntrInfo::getExtractSubregInputs and TargetInstrInfo::getExtractSubregLikeInputs to specify that a target specific instruction is a (kind of) EXTRACT_SUBREG. The approach is similar to r215394. <rdar://problem/12702965> llvm-svn: 216130
2014-08-11Add isRegSequence property.Quentin Colombet1-0/+1
This patch adds a new property: isRegSequence and the related target hooks: TargetIntrInfo::getRegSequenceInputs and TargetInstrInfo::getRegSequenceLikeInputs to specify that a target specific instruction is a (kind of) REG_SEQUENCE. <rdar://problem/12702965> llvm-svn: 215394
2014-08-01Make getNamedOperandIdx readonlyMatt Arsenault1-0/+1
llvm-svn: 214524
2014-04-30[C++11] Use 'nullptr' in tablegen output files.Craig Topper1-5/+5
llvm-svn: 207611
2014-04-18c++11: Tidy up tblgen w/ range loops.Jim Grosbach1-62/+53
IntrInfoEmitter cleanup. llvm-svn: 206553
2014-02-05Fix a vector that was passed by value instead of reference.Craig Topper1-5/+5
llvm-svn: 200827
2013-11-19[weak vtables] Remove a bunch of weak vtablesJuergen Ributzka1-4/+6
This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. The memory leaks in this version have been fixed. Thanks Alexey for pointing them out. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 195064
2013-11-18Revert r194865 and r194874.Alexey Samsonov1-6/+4
This change is incorrect. If you delete virtual destructor of both a base class and a subclass, then the following code: Base *foo = new Child(); delete foo; will not cause the destructor for members of Child class. As a result, I observe plently of memory leaks. Notable examples I investigated are: ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl. llvm-svn: 194997
2013-11-17TableGen: Generate an enum for all named Operand types in tblgen'd InstrInfo.Ahmed Bougacha1-0/+31
llvm-svn: 194978
2013-11-15[weak vtables] Remove a bunch of weak vtablesJuergen Ributzka1-4/+6
This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 194865
2013-09-12Add an instruction deprecation feature to TableGen.Joey Gouly1-0/+13
The 'Deprecated' class allows you to specify a SubtargetFeature that the instruction is deprecated on. The 'ComplexDeprecationPredicate' class allows you to define a custom predicate that is called to check for deprecation. For example: ComplexDeprecationPredicate<"MCR"> would mean you would have to define the following function: bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) Which returns 'false' for not deprecated, and 'true' for deprecated and store the warning message in 'Info'. The MCTargetAsmParser constructor was chaned to take an extra argument of the MCInstrInfo class, so out-of-tree targets will need to be changed. llvm-svn: 190598
2013-09-03TableGen: Enumerate Schedule Model too.Vincent Lejeune1-1/+9
llvm-svn: 189839
2013-08-22ARM: use TableGen patterns to select CMOV operations.Tim Northover1-2/+2
Back in the mists of time (2008), it seems TableGen couldn't handle the patterns necessary to match ARM's CMOV node that we convert select operations to, so we wrote a lot of fairly hairy C++ to do it for us. TableGen can deal with it now: there were a few minor differences to CodeGen (see tests), but nothing obviously worse that I could see, so we should probably address anything that *does* come up in a localised manner. llvm-svn: 188995
2013-07-31Revert "TableGen: Enumerate Schedule Model too."Tom Stellard1-7/+0
This reverts commit 2ca1e4a39c7e0d7a00e66ff5437c6d7ace2404a0. llvm-svn: 187525
2013-07-31TableGen: Enumerate Schedule Model too.Vincent Lejeune1-0/+7
llvm-svn: 187511
2013-07-15Teaching llvm-tblgen to not emit a switch statement when there are no case ↵Aaron Ballman1-23/+30
statements. llvm-svn: 186330
2013-06-25TableGen: Generate a function for getting operand indices based on their ↵Tom Stellard1-0/+130
defined names This patch modifies TableGen to generate a function in ${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used to look up indices for operands based on their names. In order to activate this feature for an instruction, you must set the UseNamedOperandTable bit. For example, if you have an instruction like: def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>; You can look up the operand indices using the new function, like this: Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0 Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1 Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2 The operand names are case sensitive, so $dst and $DST are considered different operands. This change is useful for R600 which has instructions with a large number of operands, many of which model single bit instruction configuration values. These configuration bits are common across most instructions, but may have a different operand index depending on the instruction type. It is useful to have a convenient way to look up the operand indices, so these bits can be generically set on any instruction. llvm-svn: 184879
2012-12-04Sort the #include lines for utils/...Chandler Carruth1-1/+1
I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
2012-11-28Remove all references to TargetInstrInfoImpl.Jakob Stoklund Olesen1-2/+2
This class has been merged into its super-class TargetInstrInfo. llvm-svn: 168760
2012-10-25Remove exception handling usage from tblgen.Joerg Sonnenberger1-2/+4
Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. llvm-svn: 166712
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