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path: root/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp
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2014-12-13Use range-based for loops.Craig Topper1-52/+35
llvm-svn: 224187
2014-09-27Reduce code duplication a bit.Craig Topper1-16/+10
llvm-svn: 218563
2014-09-27Fix TableGen -gen-disassembler output for bit fields with an offset.Craig Topper1-1/+5
This fixes bit assignments like this Inst{7-0} = Foo{9-2} Patch by Steve King. llvm-svn: 218560
2014-09-04Use vector constructor instead of a for loop to initialize entries.Craig Topper1-4/+2
llvm-svn: 217123
2014-09-03Fix ambiguous call to make_unique and clang-format.Yaron Keren1-13/+7
llvm-svn: 217023
2014-09-03Recommit "Use unique_ptr to manager FilterChooser ownership."Craig Topper1-23/+16
Just using insert of a pair this time instead of emplace. llvm-svn: 217018
2014-09-03Revert "Use unique_ptr to manager FilterChooser ownership."Craig Topper1-15/+24
std::map::emplace isn't working on some of the bots. llvm-svn: 217015
2014-09-03Use unique_ptr to manager FilterChooser ownership.Craig Topper1-24/+15
llvm-svn: 217014
2014-09-03Implement move constructor and remove copy constructor for Filter objects in ↵Craig Topper1-13/+8
FixedLenDecoderEmitter. Also remove unused copy constructor of FilterChooser. llvm-svn: 217013
2014-04-22[Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth1-2/+2
definition below all of the header #include lines, TableGen edition. llvm-svn: 206846
2014-04-15[C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper1-7/+7
instead of comparing to nullptr. llvm-svn: 206254
2014-03-13[TableGen] Optionally forbid overlap between named and positional operandsHal Finkel1-1/+16
There are currently two schemes for mapping instruction operands to instruction-format variables for generating the instruction encoders and decoders for the assembler and disassembler respectively: a) to map by name and b) to map by position. In the long run, we'd like to remove the position-based scheme and use only name-based mapping. Unfortunately, the name-based scheme currently cannot deal with complex operands (those with suboperands), and so we currently must use the position-based scheme for those. On the other hand, the position-based scheme cannot deal with (register) variables that are split into multiple ranges. An upcoming commit to the PowerPC backend (adding VSX support) will require this capability. While we could teach the position-based scheme to handle that, since we'd like to move away from the position-based mapping generally, it seems silly to teach it new tricks now. What makes more sense is to allow for partial transitioning: use the name-based mapping when possible, and only use the position-based scheme when necessary. Now the problem is that mixing the two sensibly was not possible: the position-based mapping would map based on position, but would not skip those variables that were mapped by name. Instead, the two sets of assignments would overlap. However, I cannot currently change the current behavior, because there are some backends that rely on it [I think mistakenly, but I'll send a message to llvmdev about that]. So I've added a new TableGen bit variable: noNamedPositionallyEncodedOperands, that can be used to cause the position-based mapping to skip variables mapped by name. llvm-svn: 203767
2014-02-09Remove unnecessary include.Craig Topper1-1/+0
llvm-svn: 201041
2014-02-09Remove some unnecessary code. The conditions it was checking had already ↵Craig Topper1-7/+0
been ruled out by the caller. llvm-svn: 201039
2013-12-19Add support for positionally-encoded operands to FixedLenDecoderEmitterHal Finkel1-4/+156
Unfortunately, the PowerPC instruction definitions make heavy use of the positional operand encoding heuristic to map operands onto bitfield variables in the instruction definitions. Changing this to use name-based mapping is not trivial, however, because additional infrastructure needs to be designed to handle mapping of complex operands (with multiple suboperands) onto multiple bitfield variables. In the mean time, this adds support for positionally encoded operands to FixedLenDecoderEmitter, so that we can generate a disassembler for the PowerPC backend. To prevent an accidental reliance on this feature, and to prevent an undesirable interaction with existing disassemblers, a backend must opt-in to this support by setting the new decodePositionallyEncodedOperands instruction-set bit to true. When enabled, this iterates the variables that contribute to the instruction encoding, just as the encoder does, and emulates the procedure the encoder uses to map "numbered" operands to variables. The bit range for each variable is also determined as the encoder determines them. This map is then consulted during the decoder-generator's loop over operands to decode, allowing the decoder to understand both position-based and name-based operand-to-variable mappings. As noted in the comment on the decodePositionallyEncodedOperands definition, this support should be removed once it is no longer needed. There should be no change to existing disassemblers. llvm-svn: 197691
2013-12-19Add support for PointerLikeRegClass to FixedLenDecoderEmitterHal Finkel1-0/+4
This is more prep for adding the PowerPC disassembler. FixedLenDecoderEmitter should recognize PointerLikeRegClass operands as register types, and generate register-like decoding calls instead of treating them like immediates. llvm-svn: 197680
2013-12-17Support little-endian encodings in the FixedLenDecoderEmitterHal Finkel1-0/+2
The convention used to specify the PowerPC ISA is that bits are numbered in reverse order (0 is the index of the high bit). To support this "little endian" encoding convention, CodeEmitterGen will reverse the bit numberings prior to generating the encoding tables. In order to generate a disassembler, FixedLenDecoderEmitter needs to do the same. This moves the bit reversal logic out of CodeEmitterGen and into CodeGenTarget (where it can be used by both CodeEmitterGen and FixedLenDecoderEmitter). This is prep work for disassembly support in the PPC backend (which is the only in-tree user of this little-endian encoding support). llvm-svn: 197532
2013-10-01Remove several unused variables.Rafael Espindola1-1/+0
Patch by Alp Toker. llvm-svn: 191757
2013-07-15Teaching llvm-tblgen to not emit a switch statement when there are no case ↵Aaron Ballman1-8/+13
statements. llvm-svn: 186330
2012-12-26TableGen/FixedLenDecoderEmitter.cpp: Fix a potential mask overflow in ↵NAKAMURA Takumi1-1/+1
fieldFromInstruction(). Reported by Yang Yongyong, thanks! llvm-svn: 171101
2012-12-04Sort the #include lines for utils/...Chandler Carruth1-4/+3
I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
2012-10-25Remove exception handling usage from tblgen.Joerg Sonnenberger1-1/+2
Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. llvm-svn: 166712
2012-10-10tblgen: Use semantically correct RTTI functions.Sean Silva1-2/+2
Also, some minor cleanup. llvm-svn: 165647
2012-10-10tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.Sean Silva1-6/+6
Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>. That will happen in a future patch. There are also two dyn_cast_or_null<>'s slipped in instead of dyn_cast<>'s, since they were causing crashes with just dyn_cast<>. llvm-svn: 165646
2012-10-05tblgen: Replace uses of dynamic_cast<XXXRecTy> with dyn_cast<>.Sean Silva1-1/+1
This is a mechanical change of dynamic_cast<> to dyn_cast<>. A number of these uses are actually more like isa<> or cast<>, and will be changed to the semanticaly appropriate one in a future patch. llvm-svn: 165291
2012-09-17TableGen: Add initializer.Jim Grosbach1-1/+1
Keep GCC's warnings happy. It can't reason out that the state machine won't ever hit the potentially uninitialized use in OPC_FilterValue. llvm-svn: 164041
2012-09-06Re-work bit/bits value resolving in tblgenMichael Liao1-1/+1
- This patch is inspired by the failure of the following code snippet which is used to convert enumerable values into encoding bits to improve the readability of td files. class S<int s> { bits<2> V = !if(!eq(s, 8), {0, 0}, !if(!eq(s, 16), {0, 1}, !if(!eq(s, 32), {1, 0}, !if(!eq(s, 64), {1, 1}, {?, ?})))); } Later, PR8330 is found to report not exactly the same bug relevant issue to bit/bits values. - Instead of resolving bit/bits values separately through resolveBitReference(), this patch adds getBit() for all Inits and resolves bit value by resolving plus getting the specified bit. This unifies the resolving of bit with other values and removes redundant logic for resolving bit only. In addition, BitsInit::resolveReferences() is optimized to take advantage of this origanization by resolving VarBitInit's variable reference first and then getting bits from it. - The type interference in '!if' operator is revised to support possible combinations of int and bits/bit in MHS and RHS. - As there may be illegal assignments from integer value to bit, says assign 2 to a bit, but we only check this during instantiation in some cases, e.g. bit V = !if(!eq(x, 17), 0, 2); Verbose diagnostic message is generated when invalid value is resolveed to help locating the error. - PR8330 is fixed as well. llvm-svn: 163360
2012-08-17Declare some for loop indices inside the for loop statement.Craig Topper1-20/+13
llvm-svn: 162085
2012-08-17Fix up indentation of outputted decode function for readability.Craig Topper1-8/+8
llvm-svn: 162082
2012-08-15Fix a const violation in the generated disassembler.Benjamin Kramer1-2/+2
llvm-svn: 161940
2012-08-14Switch the fixed-length disassembler to be table-driven.Jim Grosbach1-281/+722
Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. llvm-svn: 161888
2012-06-11Write llvm-tblgen backends as functions instead of sub-classes.Jakob Stoklund Olesen1-1/+84
The TableGenBackend base class doesn't do much, and will be removed completely soon. Patch by Sean Silva! llvm-svn: 158311
2012-04-02Second part for the 153874 oneSilviu Baranga1-3/+3
llvm-svn: 153875
2012-03-16More const-correcting of FixedLenDecoderEmitter.Craig Topper1-13/+17
llvm-svn: 152906
2012-03-16Const-correct the FixedLenDecoderEmitter. Pass a few things by const ↵Craig Topper1-53/+58
reference instead of value to avoid some copying. llvm-svn: 152899
2012-03-16Spacing fixes. Mostly aligning arguments that spilled onto next line with ↵Craig Topper1-37/+36
the opening parenthese instead of 2 spaces in. llvm-svn: 152889
2012-03-16Remove unused field NumVariable from Filter class. Even it was needed the ↵Craig Topper1-9/+3
same result could be found with VariableInstructions.size(). Also fix some typos in comments. llvm-svn: 152885
2012-03-13Remove unused field from FixedLenDecoderEmitter. Move NumberedInstructions ↵Craig Topper1-1/+2
declaration from class to run method since its only used there and was being reinitialized anyway. llvm-svn: 152616
2012-02-29Tidy up. 80 columns.Jim Grosbach1-13/+21
llvm-svn: 151764
2012-02-09Teach the MC and disassembler about SoftFail, and hook it up to ↵James Molloy1-2/+76
UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage. llvm-svn: 150169
2012-02-05Convert assert(0) to llvm_unreachableCraig Topper1-9/+7
llvm-svn: 149814
2011-10-17Fix unused variable warning in the rare circumstance that we have no ↵Owen Anderson1-1/+4
feature-dependent instructions. llvm-svn: 142193
2011-10-01Move TableGen's parser and entry point into a libraryPeter Collingbourne1-1/+1
This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
2011-10-01Subtarget getFeatureBits() returns a uint64_t, not unsigned.Bob Wilson1-1/+1
llvm-svn: 140928
2011-09-08Make sure to handle the case where emitPredicateMatch returns false. ↵Eli Friedman1-1/+2
Noticed by inspection. llvm-svn: 139317
2011-09-08Fix warning on windows; use of comparison with bool argument.James Molloy1-1/+1
llvm-svn: 139286
2011-09-08Fix a use of freed string contents.Andrew Trick1-4/+4
Speculatively try to fix our windows testers with a patch I found on the internet. llvm-svn: 139279
2011-09-08whitespaceAndrew Trick1-2/+2
llvm-svn: 139278
2011-09-07Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds ↵James Molloy1-4/+52
predicate checking to the Disassembler. llvm-svn: 139250
2011-08-17Allow the MCDisassembler to return a "soft fail" status code, indicating an ↵Owen Anderson1-16/+22
instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. Patch by James Molloy. llvm-svn: 137830
generated by cgit v1.1 at 2025-10-19 00:42:25 +0000