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path: root/llvm/utils/TableGen/DisassemblerEmitter.cpp
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2014-05-06AArch64/ARM64: implement diagnosis of unpredictable loads & storesTim Northover1-4/+7
llvm-svn: 208091
2014-01-05Don't use PrintFatalError(which calls exit) for 'Primary decode conflict'. ↵Craig Topper1-3/+4
Just skip emitting the table. This way the main function will delete the output file instead of it remaining empty and confusing dependency checks if build is invoked a second time. llvm-svn: 198529
2013-01-31Add AArch64 as an experimental target.Tim Northover1-2/+3
This patch adds support for AArch64 (ARM's 64-bit architecture) to LLVM in the "experimental" category. Currently, it won't be built unless requested explicitly. This initial commit should have support for: + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions (except the late addition CRC instructions). + CodeGen features required for C++03 and C99. + Compilation for the "small" memory model: code+static data < 4GB. + Absolute and position-independent code. + GNU-style (i.e. "__thread") TLS. + Debugging information. The principal omission, currently, is performance tuning. This patch excludes the NEON support also reviewed due to an outbreak of batshit insanity in our legal department. That will be committed soon bringing the changes to precisely what has been approved. Further reviews would be gratefully received. llvm-svn: 174054
2012-10-25Remove exception handling usage from tblgen.Joerg Sonnenberger1-4/+2
Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. llvm-svn: 166712
2012-06-11Write llvm-tblgen backends as functions instead of sub-classes.Jakob Stoklund Olesen1-21/+26
The TableGenBackend base class doesn't do much, and will be removed completely soon. Patch by Sean Silva! llvm-svn: 158311
2011-11-09Remove the old-style ARM disassembler, which is no longer used.Owen Anderson1-1/+0
llvm-svn: 144243
2011-10-01Move TableGen's parser and entry point into a libraryPeter Collingbourne1-2/+2
This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
2011-09-07Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds ↵James Molloy1-2/+3
predicate checking to the Disassembler. llvm-svn: 139250
2011-09-01Fix up r137380 based on post-commit review by Jim Grosbach.James Molloy1-3/+3
llvm-svn: 138948
2011-08-17Allow the MCDisassembler to return a "soft fail" status code, indicating an ↵Owen Anderson1-0/+10
instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. Patch by James Molloy. llvm-svn: 137830
2011-08-09Replace the existing ARM disassembler with a new one based on the ↵Owen Anderson1-7/+0
FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-06-21Consolidate some TableGen diagnostic helper functions.Jim Grosbach1-0/+1
TableGen had diagnostic printers sprinkled about in a few places. Pull them together into a single location in Error.cpp. llvm-svn: 133568
2011-04-04Add support for the VIA PadLock instructions.Joerg Sonnenberger1-6/+6
llvm-svn: 128826
2011-02-18Add FixedLenDecoderEmitter, the skeleton of a new disassembler emitter for ↵Owen Anderson1-2/+3
fixed-length instruction encodings. A major part of its (eventual) goal is to support a much cleaner separation between disassembly callbacks provided by the target and the disassembler emitter itself, i.e. not requiring hardcoding of knowledge in tblgen like the existing disassembly emitters do. The hope is that some day this will allow us to replace the existing non-Thumb ARM disassembler and remove some of the hacks the old one introduced to tblgen. llvm-svn: 125966
2010-12-13eliminate the Records global variable, patch by Garrison Venn!Chris Lattner1-1/+1
llvm-svn: 121659
2010-04-02Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgenJohnny Chen1-0/+8
backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-03-19change Target.getInstructionsByEnumValue to return a referenceChris Lattner1-2/+2
to a vector that CGT stores instead of synthesizing it on every call. llvm-svn: 98910
2010-03-16--- Reverse-merging r98637 into '.':Bob Wilson1-8/+0
U test/CodeGen/ARM/tls2.ll U test/CodeGen/ARM/arm-negative-stride.ll U test/CodeGen/ARM/2009-10-30.ll U test/CodeGen/ARM/globals.ll U test/CodeGen/ARM/str_pre-2.ll U test/CodeGen/ARM/ldrd.ll U test/CodeGen/ARM/2009-10-27-double-align.ll U test/CodeGen/Thumb2/thumb2-strb.ll U test/CodeGen/Thumb2/ldr-str-imm12.ll U test/CodeGen/Thumb2/thumb2-strh.ll U test/CodeGen/Thumb2/thumb2-ldr.ll U test/CodeGen/Thumb2/thumb2-str_pre.ll U test/CodeGen/Thumb2/thumb2-str.ll U test/CodeGen/Thumb2/thumb2-ldrh.ll U utils/TableGen/TableGen.cpp U utils/TableGen/DisassemblerEmitter.cpp D utils/TableGen/RISCDisassemblerEmitter.h D utils/TableGen/RISCDisassemblerEmitter.cpp U Makefile.rules U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/Makefile U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h D lib/Target/ARM/Disassembler U lib/Target/ARM/ARMInstrFormats.td U lib/Target/ARM/ARMAddressingModes.h U lib/Target/ARM/Thumb2ITBlockPass.cpp llvm-svn: 98640
2010-03-16Initial ARM/Thumb disassembler check-in. It consists of a tablgen backendJohnny Chen1-0/+8
(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] llvm-svn: 98637
2009-12-19Table-driven disassembler for the X86 architecture (16-, 32-, and 64-bit Sean Callanan1-0/+99
incarnations), integrated into the MC framework. The disassembler is table-driven, using a custom TableGen backend to generate hierarchical tables optimized for fast decode. The disassembler consumes MemoryObjects and produces arrays of MCInsts, adhering to the abstract base class MCDisassembler (llvm/MC/MCDisassembler.h). The disassembler is documented in detail in - lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime) - utils/TableGen/DisassemblerEmitter.cpp (table emitter) You can test the disassembler by running llvm-mc -disassemble for i386 or x86_64 targets. Please let me know if you encounter any problems with it. llvm-svn: 91749
2009-11-25Sketch TableGen disassembler emitter, based on patch by Sean Callanan.Daniel Dunbar1-0/+30
llvm-svn: 89833
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