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path: root/llvm/utils/TableGen/CodeGenTarget.h
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2016-08-11Use the range variant of find instead of unpacking begin/endDavid Majnemer1-1/+1
If the result of the find is only used to compare against end(), just use is_contained instead. No functionality change is intended. llvm-svn: 278433
2016-05-25TableGen: Use StringRef instead of std::stringMatt Arsenault1-2/+2
llvm-svn: 270741
2016-01-17[TableGen] Replace instructions() with getInstructionsByEnumValue(). No need ↵Craig Topper1-3/+0
to make an iterator_range when we already have a function that returns an ArrayRef. NFC llvm-svn: 258019
2016-01-17[TableGen] Return ArrayRef instead of a std::vector reference from ↵Craig Topper1-2/+2
getInstructionsByEnumValue(). NFC llvm-svn: 258018
2016-01-17[TableGen] Use std::find instead of a manual loop. NFCCraig Topper1-3/+1
llvm-svn: 258017
2015-12-06Use make_range to reduce mentions of iterator type. NFCCraig Topper1-1/+1
llvm-svn: 254872
2014-12-10Use unique_ptr instead of DeleteContainerSeconds.Craig Topper1-4/+5
llvm-svn: 223918
2014-11-28Use unique_ptr to simplify deletion.Craig Topper1-2/+2
llvm-svn: 222929
2014-08-13Canonicalize header guards into a common format.Benjamin Kramer1-2/+2
Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
2014-04-18iterator_range accessor for CodeGenTarget instruction list.Jim Grosbach1-0/+3
llvm-svn: 206551
2013-12-17Support little-endian encodings in the FixedLenDecoderEmitterHal Finkel1-0/+4
The convention used to specify the PowerPC ISA is that bits are numbered in reverse order (0 is the index of the high bit). To support this "little endian" encoding convention, CodeEmitterGen will reverse the bit numberings prior to generating the encoding tables. In order to generate a disassembler, FixedLenDecoderEmitter needs to do the same. This moves the bit reversal logic out of CodeEmitterGen and into CodeGenTarget (where it can be used by both CodeEmitterGen and FixedLenDecoderEmitter). This is prep work for disassembly support in the PPC backend (which is the only in-tree user of this little-endian encoding support). llvm-svn: 197532
2013-03-17Use ArrayRef<MVT::SimpleValueType> when possible.Jakob Stoklund Olesen1-3/+3
Not passing vector references around makes it possible to use SmallVector in most places. llvm-svn: 177235
2012-12-04Sort the #include lines for utils/...Chandler Carruth1-2/+2
I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
2012-10-25Remove exception handling usage from tblgen.Joerg Sonnenberger1-2/+2
Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. llvm-svn: 166712
2012-08-23Add CodeGenTarget::guessInstructionProperties.Jakob Stoklund Olesen1-0/+4
Currently, TableGen just guesses instruction properties when it can't infer them form patterns. This adds a guessInstructionProperties flag to the instruction set definition that will be used to disable guessing. The flag is intended as a migration aid. It will be removed again when no more targets need their properties guessed. llvm-svn: 162460
2012-07-07I'm introducing a new machine model to simultaneously allow simpleAndrew Trick1-1/+7
subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
2012-03-01Revert "Emit the SubRegTable with the smallest possible integer type."Jim Grosbach1-4/+0
This reverts commit 151760. We want to move getSubReg() from TargetRegisterInfo into MCRegisterInfo, but to do that, the type of the lookup table needs to be the same for all targets. llvm-svn: 151814
2012-02-29Emit the SubRegTable with the smallest possible integer type.Benjamin Kramer1-0/+4
Doesn't help ARM with its massive register set, but halves the size on x86 and all other targets. llvm-svn: 151760
2012-01-09Split AsmParser into two components - AsmParser and AsmParserVariantDevang Patel1-0/+10
AsmParser holds info specific to target parser. AsmParserVariant holds info specific to asm variants supported by the target. llvm-svn: 147787
2011-10-01Move TableGen's parser and entry point into a libraryPeter Collingbourne1-1/+1
This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
2011-09-29Switch to ArrayRef<CodeGenRegisterClass*>.Jakob Stoklund Olesen1-4/+0
This makes it possible to allocate CodeGenRegisterClass instances dynamically and reorder them. llvm-svn: 140816
2011-06-27Add support for alternative register names, useful for instructions whose ↵Owen Anderson1-0/+7
operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0. Patch by Jim Grosbach. llvm-svn: 133940
2011-06-18Store CodeGenRegisters as pointers so they won't be reallocated.Jakob Stoklund Olesen1-4/+0
Reuse the CodeGenRegBank DenseMap in a few places that would build their own or use linear search. llvm-svn: 133333
2011-06-15Move the list of register classes into CodeGenRegBank as well.Jakob Stoklund Olesen1-64/+2
No functional change intended. llvm-svn: 133029
2011-06-11Move the list of registers into CodeGenRegBank.Jakob Stoklund Olesen1-4/+1
Also move the sub-register index computations from RegisterInfoEmitter into CodeGenRegBank. llvm-svn: 132865
2011-06-10Move some sub-register index calculations to CodeGenRegisters.cppJakob Stoklund Olesen1-19/+4
Create a new CodeGenRegBank class that will eventually hold all the code that computes the register structure from Records. llvm-svn: 132849
2011-05-07Teach TableGen to automatically generate missing SubRegIndex instances.Jakob Stoklund Olesen1-0/+3
The RegisterInfo.td file should only specify the indexes that sources need to refer to. The rest is inferred. llvm-svn: 131058
2011-03-11Trailing whitespace.Jim Grosbach1-13/+13
llvm-svn: 127447
2010-12-23Flag -> Glue, the ongoing sagaChris Lattner1-3/+3
llvm-svn: 122513
2010-12-13eliminate the Records global variable, patch by Garrison Venn!Chris Lattner1-1/+2
llvm-svn: 121659
2010-11-02a bunch of random cleanup, move a helper to CGT where it belongs.Chris Lattner1-0/+4
llvm-svn: 118031
2010-09-21fix a long standing wart: all the ComplexPattern's were beingChris Lattner1-1/+3
passed the root of the match, even though only a few patterns actually needed this (one in X86, several in ARM [which should be refactored anyway], and some in CellSPU that I don't feel like detangling). Instead of requiring all ComplexPatterns to take the dead root, have targets opt into getting the root by putting SDNPWantRoot on the ComplexPattern. llvm-svn: 114471
2010-05-25Ignore NumberHack and give each SubRegIndex instance a unique enum value ↵Jakob Stoklund Olesen1-1/+5
instead. This passes lit tests, but I'll give it a go through the buildbots to smoke out any remaining places that depend on the old SubRegIndex numbering. Then I'll remove NumberHack entirely. llvm-svn: 104615
2010-05-24Replace the tablegen RegisterClass field SubRegClassList with an alist-like dataJakob Stoklund Olesen1-4/+14
structure that represents a mapping without any dependencies on SubRegIndex numbering. This brings us closer to being able to remove the explicit SubRegIndex numbering, and it is now possible to specify any mapping without inventing *_INVALID register classes. llvm-svn: 104563
2010-03-19add a new SDNPVariadic SDNP node flag, and use it inChris Lattner1-1/+2
dag isel gen instead of instruction properties. This allows the oh-so-useful behavior of matching a variadic non-root node. llvm-svn: 98934
2010-03-19Finally change the instruction looking map to be a densemap fromChris Lattner1-16/+11
record* -> instrinfo instead of std::string -> instrinfo. This speeds up tblgen on cellcpu from 7.28 -> 5.98s with a debug build (20%). llvm-svn: 98916
2010-03-19make inst_begin/inst_end iterate over InstructionsByEnumValue.Chris Lattner1-9/+9
Use CodeGenTarget::getInstNamespace in one place and fix it. llvm-svn: 98915
2010-03-19revert 98912Chris Lattner1-9/+9
llvm-svn: 98914
2010-03-19make inst_begin/inst_end iterate over InstructionsByEnumValue.Chris Lattner1-9/+9
llvm-svn: 98912
2010-03-19change Target.getInstructionsByEnumValue to return a referenceChris Lattner1-2/+9
to a vector that CGT stores instead of synthesizing it on every call. llvm-svn: 98910
2010-03-19don't go through getInstructions().Chris Lattner1-1/+1
llvm-svn: 98906
2010-03-19look up instructions by record, not by name.Chris Lattner1-1/+4
llvm-svn: 98904
2010-03-15Completely rewrite tblgen's type inference mechanism,Chris Lattner1-1/+1
changing the primary datastructure from being a "std::vector<unsigned char>" to being a new TypeSet class that actually has (gasp) invariants! This changes more things than I remember, but one major innovation here is that it enforces that named input values agree in type with their output values. This also eliminates code that transparently assumes (in some cases) that SDNodeXForm input/output types are the same, because this is wrong in many case. This also eliminates a bug which caused a lot of ambiguous patterns to go undetected, where a register class would sometimes pick the first possible type, causing an ambiguous pattern to get arbitrary results. With all the recent target changes, this causes no functionality change! llvm-svn: 98534
2010-01-04Remove the CPAttrParentAsRoot code, which is unused, and inconvenientDan Gohman1-5/+0
for a refactoring I'm working on. llvm-svn: 92503
2009-11-06clang++ points out that this is pointless.Chris Lattner1-1/+1
llvm-svn: 86239
2009-08-11Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson1-10/+10
while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-10Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson1-10/+10
own struct type. llvm-svn: 78610
2009-07-29Match X86 register names to number.Daniel Dunbar1-0/+4
llvm-svn: 77404
2009-07-03Replace std::iostreams with raw_ostream in TableGen.Daniel Dunbar1-1/+1
- Sorry, I can't help myself. - No intended functionality change. llvm-svn: 74742
2009-06-02Revert 72707 and 72709, for the moment.Dale Johannesen1-6/+2
llvm-svn: 72712
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