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path: root/llvm/utils/TableGen/CodeGenTarget.cpp
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2018-05-01Remove \brief commands from doxygen comments.Adrian Prantl1-1/+1
We've been running doxygen with the autobrief option for a couple of years now. This makes the \brief markers into our comments redundant. Since they are a visual distraction and we don't want to encourage more \brief markers in new code either, this patch removes them all. Patch produced by for i in $(git grep -l '\\brief'); do perl -pi -e 's/\\brief //g' $i & done Differential Revision: https://reviews.llvm.org/D46290 llvm-svn: 331272
2018-04-06[TableGen] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang1-11/+12
Summary: r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer the comments section in D44363 for a list of all the required patches. Reviewers: stoklund, kparzysz, dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45144 llvm-svn: 329451
2018-04-01TableGen: More helpful error messagesNicolai Haehnle1-2/+6
Summary: Change-Id: I3c23f6f6597912423762780cd8c5315870412bbe Reviewers: arsenm, rampitec, b-sumner Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D44936 Change-Id: Ie62614a3e2d7774f46e4034478b28f57100a2c92 llvm-svn: 328936
2018-03-23Fix layering of CodeGen/TargetOpcodes.def by moving it to SupportDavid Blaikie1-1/+1
It's also used by utils/TableGen so needs to reside somewhere common to TableGen and CodeGen. llvm-svn: 328396
2018-03-08[WebAssembly] Add except_ref as a first-class typeHeejin Ahn1-0/+1
Summary: Add except_ref as a first-class type, according to the [[https://github.com/WebAssembly/exception-handling/blob/master/proposals/Level-1.md | Level 1 exception handling proposal ]]. Reviewers: dschuff Subscribers: jfb, sbc100, llvm-commits Differential Revision: https://reviews.llvm.org/D43706 llvm-svn: 326985
2018-02-23[MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry1-0/+3
Summary: Add a target option AllowRegisterRenaming that is used to opt in to post-register-allocation renaming of registers. This is set to 0 by default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq fields of all opcodes to be set to 1, causing MachineOperand::isRenamable to always return false. Set the AllowRegisterRenaming flag to 1 for all in-tree targets that have lit tests that were effected by enabling COPY forwarding in MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC, RISCV, Sparc, SystemZ and X86). Add some more comments describing the semantics of the MachineOperand::isRenamable function and how it is set and maintained. Change isRenamable to check the operand's opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of relying on it being consistently reflected in the IsRenamable bit setting. Clear the IsRenamable bit when changing an operand's register value. Remove target code that was clearing the IsRenamable bit when changing registers/opcodes now that this is done conservatively by default. Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in one place covering all opcodes that have constant pipe read limit restrictions. Reviewers: qcolombet, MatzeB Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D43042 llvm-svn: 325931
2018-01-24[TableGen] Add a way of getting the number of generic opcodes without ↵Benjamin Kramer1-4/+11
including modular CodeGen headers. This is a bit of a hack, but removes a cycle that broke modular builds of LLVM. Of course the cycle is still there in form of a dependency on the .def file. llvm-svn: 323383
2017-12-20TableGen: Allow setting SDNodeProperties on intrinsicsMatt Arsenault1-0/+7
Allows preserving MachineMemOperands on intrinsics through selection. For reasons I don't understand, this is a static property of the pattern and the selector deliberately goes out of its way to drop if not present. Intrinsics already inherit from SDPatternOperator allowing them to be used directly in instruction patterns. SDPatternOperator has a list of SDNodeProperty, but you currently can't set them on the intrinsic. Without SDNPMemOperand, when the node is selected any memory operands are always dropped. Allowing setting this on the intrinsics avoids needing to introduce another equivalent target node just to have SDNPMemOperand set. llvm-svn: 321212
2017-12-14Add MVT::v128i1, NFCKrzysztof Parzyszek1-0/+1
Hexagon HVX has type v128i8, comparing two vectors of that type will produce v128i1 types in SelectionDAG. llvm-svn: 320732
2017-11-17Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie1-1/+1
All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
2017-09-14TableGen support for parameterized register class informationKrzysztof Parzyszek1-8/+8
This replaces TableGen's type inference to operate on parameterized types instead of MVTs, and as a consequence, some interfaces have changed: - Uses of MVTs are replaced by ValueTypeByHwMode. - EEVT::TypeSet is replaced by TypeSetByHwMode. This affects the way that types and type sets are printed, and the tests relying on that have been updated. There are certain users of the inferred types outside of TableGen itself, namely FastISel and GlobalISel. For those users, the way that the types are accessed have changed. For typical scenarios, these replacements can be used: - TreePatternNode::getType(ResNo) -> getSimpleType(ResNo) - TreePatternNode::hasTypeSet(ResNo) -> hasConcreteType(ResNo) - TypeSet::isConcrete -> TypeSetByHwMode::isValueTypeByHwMode(false) For more information, please refer to the review page. Differential Revision: https://reviews.llvm.org/D31951 llvm-svn: 313271
2017-07-07[TableGen] Use StringRef instead of std::string for CodeGenInstruction ↵Craig Topper1-1/+1
namespace. NFC llvm-svn: 307362
2017-05-18[MVT] add v1i1 MVTGuy Blank1-0/+2
Adds the v1i1 MVT as a preparation for another commit (https://reviews.llvm.org/D32273) Differential Revision: https://reviews.llvm.org/D32540 llvm-svn: 303346
2017-04-28TableGen: Add IntrHasSideEffects property for intrinsicsMatt Arsenault1-0/+3
The IntrNoMem, IntrReadMem, IntrWriteMem, and IntrArgMemOnly intrinsic properties differ from their corresponding LLVM IR attributes by specifying that the intrinsic, in addition to its memory properties, has no other side effects. The IntrHasSideEffects flag used in combination with one of the memory flags listed above, makes it possible to define an intrinsic such that its properties at the CodeGen layer match its properties at the IR layer. Patch by Tom Stellard llvm-svn: 301685
2017-04-28Add speculatable function attributeMatt Arsenault1-0/+3
This attribute tells the optimizer that the function may be speculated. Patch by Tom Stellard llvm-svn: 301680
2017-04-20[MVT][SVE] Scalable vector MVTs (2/3)Amara Emerson1-0/+39
Adds scalable vector machine value types, and updates the switch statements required for tablegen. Patch by Graham Hunter. Differential Revision: https://reviews.llvm.org/D32018 llvm-svn: 300840
2017-03-27[tablegen] Use categories on options that only matter to one emitter.Daniel Sanders1-4/+9
Summary: The categories are emitted in a strange order in this patch due to a bug in the CommandLine library. Reviewers: ab Reviewed By: ab Subscribers: ab, llvm-commits Differential Revision: https://reviews.llvm.org/D30995 llvm-svn: 298843
2016-12-04TableGen: Use StringRef instead of const std::string& in return vals.Matthias Braun1-2/+2
This will allow to switch to a different string storage in an upcoming commit. llvm-svn: 288612
2016-11-22Add IntrInaccessibleMemOnly property for intrinsicsAndrew Kaylor1-1/+6
Differential Revision: https://reviews.llvm.org/D26485 llvm-svn: 287680
2016-11-09Re-apply r286384, "X86: Introduce the "relocImm" ComplexPattern, which ↵Peter Collingbourne1-0/+10
represents a relocatable immediate.", with a fix for 32-bit x86. Teach X86InstrInfo::analyzeCompare() not to crash on CMP and SUB instructions that take a global address operand. llvm-svn: 286420
2016-11-09Revert r286384, "X86: Introduce the "relocImm" ComplexPattern, which ↵Peter Collingbourne1-10/+0
represents a relocatable immediate." Suspected to be the cause of a sanitizer-windows bot failure: Assertion failed: isImm() && "Wrong MachineOperand accessor", file C:\b\slave\sanitizer-windows\llvm\include\llvm/CodeGen/MachineOperand.h, line 420 llvm-svn: 286385
2016-11-09X86: Introduce the "relocImm" ComplexPattern, which represents a relocatable ↵Peter Collingbourne1-0/+10
immediate. A relocatable immediate is either an immediate operand or an operand that can be relocated by the linker to an immediate, such as a regular symbol in non-PIC code. Start using relocImm for 32-bit and 64-bit MOV instructions, and for operands of type "imm32_su". Remove a number of now-redundant patterns. Differential Revision: https://reviews.llvm.org/D25812 llvm-svn: 286384
2016-11-03Expandload and Compressstore intrinsicsElena Demikhovsky1-2/+1
2 new intrinsics covering AVX-512 compress/expand functionality. This implementation includes syntax, DAG builder, operation lowering and tests. Does not include: handling of illegal data types, codegen prepare pass and the cost model. llvm-svn: 285876
2016-07-20GlobalISel: Remove explicit enumerator values from .def file.Tim Northover1-1/+1
They were all auto-incremented from 0 anyway, and I'm getting really annoying conflicts and runtime failures when different people add more for GlobalISel (and even when I'm refactoring my own patches). NFC. llvm-svn: 276204
2016-07-15IR: Sort generic intrinsics before target specific onesJustin Bogner1-9/+15
This splits out the intrinsic table such that generic intrinsics come first and target specific intrinsics are grouped by target. From here we can find out which target an intrinsic is for or differentiate between generic and target intrinsics. The motivation here is to make it easier to move target specific intrinsic handling out of generic code. llvm-svn: 275575
2016-07-14TableGen: Fix a confusing use of both i and I as variables. NFCJustin Bogner1-5/+5
llvm-svn: 275450
2016-07-11Add a 'Returned' intrinsic property corresponding to the 'returned' argument ↵Hal Finkel1-0/+3
attribute This will be used by the upcoming llvm.noalias intrinsic. Differential Revision: http://reviews.llvm.org/D22201 llvm-svn: 275034
2016-07-04Add writeonly IR attributeNicolai Haehnle1-0/+3
Summary: This complements the earlier addition of IntrWriteMem and IntrWriteArgMem LLVM intrinsic properties, see D18291. Also start using the attribute for memset, memcpy, and memmove intrinsics, and remove their special-casing in BasicAliasAnalysis. Reviewers: reames, joker.eph Subscribers: joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D18714 llvm-svn: 274485
2016-05-25TableGen: Use StringRef instead of std::stringMatt Arsenault1-2/+2
llvm-svn: 270741
2016-04-21Split IntrReadArgMem into IntrReadMem and IntrArgMemOnlyNicolai Haehnle1-8/+4
Summary: IntrReadWriteArgMem simply becomes IntrArgMemOnly. So there are fewer intrinsic properties that express their orthogonality better, and correspond more closely to the corresponding IR attributes. Suggested by: Philip Reames Reviewers: joker.eph, reames, tstellarAMD Subscribers: jholewinski, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19291 llvm-svn: 267021
2016-04-19Add IntrWrite[Arg]Mem intrinsic propertyNicolai Haehnle1-0/+4
Summary: This property is used to mark an intrinsic that only writes to memory, but neither reads from memory nor has other side effects. An example where this is useful is the llvm.amdgcn.buffer.store.format.* intrinsic, which corresponds to a store instruction that goes through a special buffer descriptor rather than through a plain pointer. With this property, the intrinsic should still be handled as having side effects at the LLVM IR level, but machine scheduling can make smarter decisions. Reviewers: tstellarAMD, arsenm, joker.eph, reames Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18291 llvm-svn: 266826
2016-04-12Minor code cleanup. NFC.Junmo Park1-2/+2
llvm-svn: 266045
2016-02-10SelectionDAG: Make Properties a field of SDPatternOperatorMatt Arsenault1-1/+1
Currently you can't specify node properties like commutativity on a PatFrag. If you want to create a PatFrag on a commutative node with a hasOneUse predicate, this enables you to specify that the PatFrag is also commutable. llvm-svn: 260404
2016-02-03Unify the target opcode enum in TargetOpcodes.h and the FixedInstrs array inDavid L Kreitzer1-12/+2
CodeGenTarget.cpp to avoid the ordering dependence. NFCI. Differential Revision: http://reviews.llvm.org/D16826 llvm-svn: 259726
2016-02-03Minor performance tweaks to llvm-tblgen (and a few that might be a good idea)Reid Kleckner1-1/+2
Summary: This patch adds a reserve call to an expensive function (`llvm::LoadIntrinsics`), and may fix a few other low hanging performance fruit (I've put them in comments for now, so we can discuss). **Motivation:** As I'm sure other developers do, when I build LLVM, I build the entire project with the same config (`Debug`, `MinSizeRel`, `Release`, or `RelWithDebInfo`). However, the `Debug` config also builds llvm-tblgen in `Debug` mode. Later build steps that run llvm-tblgen then can actually be the slowest steps in the entire build. Nobody likes slow builds. Reviewers: rnk, dblaikie Differential Revision: http://reviews.llvm.org/D16832 Patch by Alexander G. Riccio llvm-svn: 259683
2016-01-26Sort intrinsics by LLVM intrinsic name, rather than tablegen def nameReid Kleckner1-0/+4
Step one towards using a simple binary search to lookup intrinsic IDs instead of our crazy table generated switch+memcmp+startswith code that makes Function.cpp take about a minute to compile. See PR24785 and PR11951 for why we should do this. The X86 backend contains tables that need to be sorted on intrinsic ID, so reorder those. llvm-svn: 258757
2016-01-20[GlobalISel] Add a generic machine opcode for ADD.Quentin Colombet1-0/+5
The selection process being split into separate passes, we need generic opcodes to translate the LLVM IR to target independent code. This patch adds an opcode for addition: G_ADD. Differential Revision: http://reviews.llvm.org/D15472 llvm-svn: 258333
2016-01-17[TableGen] Replace instructions() with getInstructionsByEnumValue(). No need ↵Craig Topper1-1/+1
to make an iterator_range when we already have a function that returns an ArrayRef. NFC llvm-svn: 258019
2015-11-24Add names for the new vector types in CodeGenTarget.cppKrzysztof Parzyszek1-0/+9
llvm-svn: 253989
2015-11-24Revert change that accidentally snuck into r253955.Craig Topper1-2/+1
llvm-svn: 253956
2015-11-24[TableGen] Use array_pod_sort. NFCCraig Topper1-2/+3
llvm-svn: 253955
2015-09-02[TableGen] Allow TokenTy in intrinsic signaturesJoseph Tremoulet1-0/+1
Summary: Add the necessary plumbing so that llvm_token_ty can be used as an argument/return type in intrinsic definitions and correspondingly require TokenTy in function types. TokenTy is an opaque type that has no target lowering, but can be used in machine-independent intrinsics. It is required for the upcoming llvm.eh.padparam intrinsic. Reviewers: majnemer, rnk Subscribers: stoklund, llvm-commits Differential Revision: http://reviews.llvm.org/D12532 llvm-svn: 246651
2015-07-07Rename llvm.frameescape and llvm.framerecover to localescape and localrecoverReid Kleckner1-1/+1
Summary: Initially, these intrinsics seemed like part of a family of "frame" related intrinsics, but now I think that's more confusing than helpful. Initially, the LangRef specified that this would create a new kind of allocation that would be allocated at a fixed offset from the frame pointer (EBP/RBP). We ended up dropping that design, and leaving the stack frame layout alone. These intrinsics are really about sharing local stack allocations, not frame pointers. I intend to go further and add an `llvm.localaddress()` intrinsic that returns whatever register (EBP, ESI, ESP, RBX) is being used to address locals, which should not be confused with the frame pointer. Naming suggestions at this point are welcome, I'm happy to re-run sed. Reviewers: majnemer, nicholas Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11011 llvm-svn: 241633
2015-06-15[CodeGen] Introduce a FAULTING_LOAD_OP pseudo-op.Sanjoy Das1-1/+1
Summary: This instruction encodes a loading operation that may fault, and a label to branch to if the load page-faults. The locations of potentially faulting loads and their "handler" destinations are recorded in a FaultMap section, meant to be consumed by LLVM's clients. Nothing generates FAULTING_LOAD_OP instructions yet, but they will be used in a future change. The documentation (FaultMaps.rst) needs improvement and I will update this diff with a more expanded version shortly. Depends on D10196 Reviewers: rnk, reames, AndyAyers, ab, atrick, pgavlin Reviewed By: atrick, pgavlin Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10197 llvm-svn: 239740
2015-06-02[TableGen] Rename ListInit::getSize to just 'size' to be more consistent.Craig Topper1-3/+3
llvm-svn: 238806
2015-05-26Add initial support for the convergent attribute.Owen Anderson1-0/+3
llvm-svn: 238264
2015-05-11Fix tablegen's PrintFatalError function to run registered fileJames Y Knight1-3/+3
cleanups. Also, change code in tablegen which printed a message and then called "exit(1)" to use PrintFatalError, instead. This fixes instances where an empty output file was left behind after a failed tablegen invocation, which would confuse subsequent ninja runs into not attempting to rebuild. Differential Revision: http://reviews.llvm.org/D9608 llvm-svn: 237058
2015-04-17Add support for v1i128 type.Kit Barton1-0/+1
The v1i128 type is needed for the quadword add/substract instructions introduced in POWER8. Futhermore, the PowerPC ABI specifies that parameters of type v1i128 are to be passed in a single vector register, while parameters of type i128 are passed in pairs of GPRs. Thus, it is necessary to be able to differentiate between v1i128 and i128 in LLVM. http://reviews.llvm.org/D8564 llvm-svn: 235198
2015-01-22Intrinsics: introduce llvm_any_ty aka ValueType AnyRamkumar Ramachandra1-0/+1
Specifically, gc.result benefits from this greatly. Instead of: gc.result.int.* gc.result.float.* gc.result.ptr.* ... We now have a gc.result.* that can specialize to literally any type. Differential Revision: http://reviews.llvm.org/D7020 llvm-svn: 226857
2015-01-13Add the llvm.frameallocate and llvm.recoverframeallocation intrinsicsReid Kleckner1-1/+1
These intrinsics allow multiple functions to share a single stack allocation from one function's call frame. The function with the allocation may only perform one allocation, and it must be in the entry block. Functions accessing the allocation call llvm.recoverframeallocation with the function whose frame they are accessing and a frame pointer from an active call frame of that function. These intrinsics are very difficult to inline correctly, so the intention is that they be introduced rarely, or at least very late during EH preparation. Reviewers: echristo, andrew.w.kaylor Differential Revision: http://reviews.llvm.org/D6493 llvm-svn: 225746
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