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2020-01-24TableGen: Work around assert on Mips register definitionsMatt Arsenault1-2/+8
This would hit the "Biggest class wasn't first" assert in getMatchingSubClassWithSubRegs in a future patch for EXTRACT_SUBREG handling. Mips defines 4 identical register classes (MSA128B, MSA128H, MSA128BW, MSA128D). These have the same set of registers, and only differ by the isel type. I believe this is an ill formed way of defining registers, that probably is just to work around the inconvenience of mixing different types in a single register class in DAG patterns. Since these all have the same size, they would all sort to the beginning, but you would not necessarily get the same super register at the front as the assert enforces. Breaking the ambiguity by also sorting by name doesn't work, since each of these register classes all want to be first. Force sorting of the original register class if the size is the same.
2019-09-06GlobalISel: Support physical register inputs in patternsMatt Arsenault1-0/+15
llvm-svn: 371253
2019-08-22Retire llvm::less/equal in favor of C++14 std::less<>/equal_to<>.Benjamin Kramer1-8/+10
llvm-svn: 369674
2019-08-15[llvm] Migrate llvm::make_unique to std::make_uniqueJonas Devlieghere1-2/+2
Now that we've moved to C++14, we no longer need the llvm::make_unique implementation from STLExtras.h. This patch is a mechanical replacement of (hopefully) all the llvm::make_unique instances across the monorepo. llvm-svn: 369013
2019-07-19[AMDGPU] Allow register tuples to set asm namesStanislav Mekhanoshin1-3/+12
This change reverts most of the previous register name generation. The real problem is that RegisterTuple does not generate asm names. Added optional operand to RegisterTuple. This way we can simplify register name access and dramatically reduce the size of static tables for the backend. Differential Revision: https://reviews.llvm.org/D64967 llvm-svn: 366598
2019-04-23Use llvm::stable_sortFangrui Song1-2/+1
While touching the code, simplify if feasible. llvm-svn: 358996
2019-02-12[tablegen] Add locations to many PrintFatalError() callsDaniel Sanders1-2/+3
Summary: While working on the GISel Combiner, I noticed I was producing location-less error messages fairly often and set about fixing this. In the process, I noticed quite a few places elsewhere in TableGen that also neglected to include a relevant location. This patch adds locations to errors that relate to a specific record (or a field within it) and also have easy access to the relevant location. This is particularly useful when multiclasses are involved as many of these errors refer to the full name of a record and it's difficult to guess which substring is grep-able. Unfortunately, tablegen currently only supports Record granularity so it's not currently possible to point at a specific Init so these sometimes point at the record that caused the error rather than the precise origin of the error. Reviewers: bogner, aditya_nandakumar, volkan, aemerson, paquette, nhaehnle Reviewed By: nhaehnle Subscribers: jdoerfert, nhaehnle, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58077 llvm-svn: 353862
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth1-4/+3
to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
2018-11-29[TableGen] Examine entire subreg compositions to detect ambiguityKrzysztof Parzyszek1-5/+59
When tablegen detects that there exist two subregister compositions that result in the same value for some register, it will emit a warning. This kind of an overlap in compositions should only happen when it is caused by a user-defined composition. It can happen, however, that the user- defined composition is not identically equal to another one, but it does produce the same value for one or more registers. In such cases suppress the warning. This patch is to silence the warning when building the System Z backend after D50725. Differential Revision: https://reviews.llvm.org/D50977 llvm-svn: 347894
2018-09-27llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)Fangrui Song1-7/+7
Summary: The convenience wrapper in STLExtras is available since rL342102. Reviewers: dblaikie, javed.absar, JDevlieghere, andreadb Subscribers: MatzeB, sanjoy, arsenm, dschuff, mehdi_amini, sdardis, nemanjai, jvesely, nhaehnle, sbc100, jgravelle-google, eraman, aheejin, kbarton, JDevlieghere, javed.absar, gbedwell, jrtc27, mgrang, atanasyan, steven_wu, george.burgess.iv, dexonsmith, kristina, jsji, llvm-commits Differential Revision: https://reviews.llvm.org/D52573 llvm-svn: 343163
2018-07-02[X86] Add phony registers for high halves of regs with low halvesKrzysztof Parzyszek1-3/+9
Add registers still missing after r328016 (D43353): - for bits 15-8 of SI, DI, BP, SP (*H), and R8-R15 (*BH), - for bits 31-16 of R8-R15 (*WH). Thanks to Craig Topper for pointing it out. llvm-svn: 336134
2018-06-08[tablegen] Improve performance on *GenRegisterInfo.inc by replacing ↵Daniel Sanders1-3/+3
SparseVector with BitVector. NFC Summary: Generating X86GenRegisterInfo.inc and AArch64GenRegisterInfo.inc is 8-9% faster on my build. Reviewers: bogner, javed.absar Reviewed By: bogner Subscribers: llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D47907 llvm-svn: 334337
2018-05-29[TableGen] Fix leaking synthesized registers.Florian Hahn1-2/+12
By keeping track of unique_ptrs to the synthesized definitions in CodeGenRegBank we avoid leaking them. Reviewers: dsanders, kparzysz, stoklund Reviewed By: dsanders Differential Revision: https://reviews.llvm.org/D47462 llvm-svn: 333434
2018-05-14Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen1-46/+43
The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
2018-04-06[TableGen] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang1-11/+11
Summary: r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer the comments section in D44363 for a list of all the required patches. Reviewers: stoklund, kparzysz, dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45144 llvm-svn: 329451
2018-03-20[X86] Add phony registers for high halves of regs with low halvesKrzysztof Parzyszek1-22/+60
Registers E[A-D]X, E[SD]I, E[BS]P, and EIP have 16-bit subregisters that cover the low halves of these registers. This change adds artificial subregisters for the high halves in order to differentiate (in terms of register units) between the 32- and the low 16-bit registers. This patch contains parts that aim to preserve the calculated register pressure. This is in order to preserve the current codegen (minimize the impact of this patch). The approach of having artificial subregisters could be used to fix PR23423, but the pressure calculation would need to be changed. Differential Revision: https://reviews.llvm.org/D43353 llvm-svn: 328016
2017-09-22[TableGen] Replace InfoByHwMode::getAsString with writeToStreamKrzysztof Parzyszek1-1/+1
Also add operator<< for use with raw_ostream to InfoByHwMode and its derived classes. Recommitting r313989 with the fix for unresolved references: explicitly define the operator<< in namespace llvm. llvm-svn: 314004
2017-09-22Revert "[TableGen] Replace InfoByHwMode::getAsString with writeToStream"Krzysztof Parzyszek1-1/+1
This reverts commit r313989: it breaks Windows bots. llvm-svn: 313990
2017-09-22[TableGen] Replace InfoByHwMode::getAsString with writeToStreamKrzysztof Parzyszek1-1/+1
Also add operator<< for use with raw_ostream to InfoByHwMode and its derived classes. llvm-svn: 313989
2017-09-21[TableGen] Tidy up CodeGenRegistersJaved Absar1-28/+23
Replacing range loops. Reviewed by: @MatzeB Differential Revision: https://reviews.llvm.org/D38091 llvm-svn: 313874
2017-09-14TableGen support for parameterized register class informationKrzysztof Parzyszek1-27/+26
This replaces TableGen's type inference to operate on parameterized types instead of MVTs, and as a consequence, some interfaces have changed: - Uses of MVTs are replaced by ValueTypeByHwMode. - EEVT::TypeSet is replaced by TypeSetByHwMode. This affects the way that types and type sets are printed, and the tests relying on that have been updated. There are certain users of the inferred types outside of TableGen itself, namely FastISel and GlobalISel. For those users, the way that the types are accessed have changed. For typical scenarios, these replacements can be used: - TreePatternNode::getType(ResNo) -> getSimpleType(ResNo) - TreePatternNode::hasTypeSet(ResNo) -> hasConcreteType(ResNo) - TypeSet::isConcrete -> TypeSetByHwMode::isValueTypeByHwMode(false) For more information, please refer to the review page. Differential Revision: https://reviews.llvm.org/D31951 llvm-svn: 313271
2017-08-28Try to fix compilation problem with libstdc++Matthias Braun1-1/+3
llvm-svn: 311918
2017-08-28Address r311914 review commentsMatthias Braun1-7/+5
llvm-svn: 311917
2017-08-28TableGen: Fix subreg composition/concatenationMatthias Braun1-27/+88
This fixes 2 problems in subregister hierarchies with multiple levels and tuples: 1) For bigger tuples computing secondary subregs would miss 2nd order effects. In the test case a register like `S10_S11_S12_S13_S14` with D5 = S10_S11, D6 = S12_S13 we would correctly compute sub0 = D5, sub1 = D6 but would miss the fact that we could now form ssub0_ssub1_ssub2_ssub3 (aka sub0_sub1) = D5_D6. This is fixed by changing computeSecondarySubRegs() to compute a fixpoint. 2) Fixing 1) exposed a problem where TableGen would create multiple names for effectively the same subregister index. In the test case the subregister index sub0 is composed from ssub0 and ssub1, and sub1 is composed from ssub2 and ssub3. TableGen should not create both sub0_sub1 and ssub0_ssub1_ssub2_ssub3 as infered subregister indexes. This changes the code to build a transitive closure of the subregister components before forming new concatenated subregister indexes. This fix was developed for an out of tree target. For the in-tree targets the only change is in the register information computed for ARM. There is a slight chance this fixed/improved some register coalescing around the QQQQ/QQ register classes there but I couldn't see/provoke any code generation differences. Differential Revision: https://reviews.llvm.org/D36913 llvm-svn: 311914
2017-07-20Implement LaneBitmask::getNumLanes and LaneBitmask::getHighestLaneKrzysztof Parzyszek1-6/+2
This should eliminate most uses of countPopulation and Log2_32 on the lane mask values. llvm-svn: 308658
2017-07-14[TableGen][MC] Fix a few places where we didn't hide the underlying type of ↵Craig Topper1-6/+6
LaneBitmask very well. One place compared with 32, which I've replaced with LaneBitmask::BitWidth. The other places are shifts of a constant 1 by a lane number. But if LaneBitmask were to be a larger type than 32-bits like 64-bits, the 1 would need to be 1ULL to do a 64-bit shift. To hide this I've added a LanebitMask::getLane that hides the shift and make sures the 1 is casted to correct type first. llvm-svn: 308042
2017-06-27Change sort function used in tblgen to be strict weak orderingDavid Green1-1/+1
The windows debug is failing as the sort function is not strict weak ordering, so switch a >= to a >. llvm-svn: 306422
2017-06-27[globalisel][tablegen] Add support for EXTRACT_SUBREG.Daniel Sanders1-0/+78
Summary: After this patch, we finally have test cases that require multiple instruction emission. Depends on D33590 Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls Subscribers: javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D33596 llvm-svn: 306388
2017-06-01[TableGen] Remove code for renaming anonymous register classes as it can ↵Craig Topper1-6/+1
never execute. It tried to detect 9 letters (the length of anonymous) followed by a period. But anonymous classes start with "anonymous_" rather than "anonymous." these days. llvm-svn: 304387
2017-03-27[TableGen] Print #nnn as a name of an non-native reg unit with id nnnKrzysztof Parzyszek1-6/+13
When using -debug with -gen-register-info, tablegen will crash when trying to print a name of a non-native register unit. This patch only affects the debug information generated while running llvm-tblgen, and has no impact on the compilable code coming out of it. llvm-svn: 298875
2016-12-16Implement LaneBitmask::any(), use it to replace !none(), NFCIKrzysztof Parzyszek1-3/+3
llvm-svn: 289974
2016-12-15Extract LaneBitmask into a separate typeKrzysztof Parzyszek1-29/+35
Specifically avoid implicit conversions from/to integral types to avoid potential errors when changing the underlying type. For example, a typical initialization of a "full" mask was "LaneMask = ~0u", which would result in a value of 0x00000000FFFFFFFF if the type was extended to uint64_t. Differential Revision: https://reviews.llvm.org/D27454 llvm-svn: 289820
2016-12-04TableGen: Use StringRef instead of const std::string& in return vals.Matthias Braun1-1/+1
This will allow to switch to a different string storage in an upcoming commit. llvm-svn: 288612
2016-11-30Fix some Clang-tidy and Include What You Use warnings; other minor fixes (NFC).Eugene Zelenko1-12/+38
This preparation to remove SetVector.h dependency on SmallSet.h. llvm-svn: 288256
2016-08-11Use the range variant of find instead of unpacking begin/endDavid Majnemer1-2/+1
If the result of the find is only used to compare against end(), just use is_contained instead. No functionality change is intended. llvm-svn: 278433
2016-04-28TableGen: Produce CoveredBySubRegs summary for register classesMatthias Braun1-2/+5
This will be used in the upcoming "DetectDeadLanes" pass. llvm-svn: 267850
2016-04-28TableGen: Support lanemasks for classes without subregistersMatthias Braun1-38/+50
Previously using lanemasks on registers without any subregisters was not well defined. This commit extends TargetRegisterInfo/tablegen to: - Report a lanemask of 1 for regclasses without subregisters - Do the right thing when mapping a 0/1 lanemask from a class without subregisters into a class with subregisters in TargetRegisterInfo::composeSubRegIndexLaneMasks(). This will be used in the upcoming "DetectDeadLanes" patch. llvm-svn: 267848
2016-01-18[TableGen] Merge the SuperClass Record and SMRange vector into a single ↵Craig Topper1-4/+3
vector. This removes the state needed to manage the extra vector thus reducing the size of the Record class. NFC llvm-svn: 258065
2015-11-17Assume lane masks are always preciseMatthias Braun1-13/+6
Allowing imprecise lane masks in case of more than 32 sub register lanes lead to some tricky corner cases, and I need another bugfix for another one. Instead I rather declare lane masks as precise and let tablegen abort if we do not have enough bits. This does not affect any in-tree target, even AMDGPU only needs 16 lanes at the moment. If the 32 lanes turn out to be a problem in the future, then we can easily change the LaneBitmask typedef to uint64_t. Differential Revision: http://reviews.llvm.org/D14557 llvm-svn: 253279
2015-11-13tablegen: Add a simple heuristic to get better names for pressure setsMatthias Braun1-0/+6
Differential Revision: http://reviews.llvm.org/D14597 llvm-svn: 253095
2015-11-10TableGen: Emit LaneMask for register classes without subregisters as ~0uMatthias Braun1-0/+6
This makes it slightly easier to handle classes with and without subregister uniformly. llvm-svn: 252671
2015-06-02[TableGen] Rename ListInit::getSize to just 'size' to be more consistent.Craig Topper1-3/+3
llvm-svn: 238806
2015-05-29Replace push_back(Constructor(foo)) with emplace_back(foo) for non-trivial typesBenjamin Kramer1-2/+2
If the type isn't trivially moveable emplace can skip a potentially expensive move. It also saves a couple of characters. Call sites were found with the ASTMatcher + some semi-automated cleanup. memberCallExpr( argumentCountIs(1), callee(methodDecl(hasName("push_back"))), on(hasType(recordDecl(has(namedDecl(hasName("emplace_back")))))), hasArgument(0, bindTemporaryExpr( hasType(recordDecl(hasNonTrivialDestructor())), has(constructExpr()))), unless(isInTemplateInstantiation())) No functional change intended. llvm-svn: 238602
2015-05-14[TableGen] Remove ListInit::size() in favor of getSize() which does the same ↵Craig Topper1-2/+2
thing and is already used in most places. NFC. llvm-svn: 237341
2015-04-24[TableGen] Don't leak Expanders and Operators in SetTheory.Craig Topper1-1/+1
llvm-svn: 235697
2015-04-15Change range-based for-loops to be -Wrange-loop-analysis clean.Richard Trieu1-1/+1
No functionality change. llvm-svn: 234963
2015-03-31Fix AllocationPriority not getting set for derived register classes.Matthias Braun1-1/+3
llvm-svn: 233752
2015-03-31RegAllocGreedy: Allow target to specify register class ordering.Matthias Braun1-0/+4
Specify an allocation order with a register class. This is used by register allocators with a greedy heuristic. This is usefull as it is sometimes beneficial to color more constrained classes first. Differential Revision: http://reviews.llvm.org/D8626 llvm-svn: 233743
2015-03-19Do not track subregister liveness when it brings no benefitsMatthias Braun1-0/+11
Some subregisters are only to indicate different access sizes, while not providing any way to actually divide the register up into multiple disjunct parts. Avoid tracking subregister liveness in these cases as it is not beneficial. Differential Revision: http://reviews.llvm.org/D8429 llvm-svn: 232695
2015-03-18TableGen: Fix register class lane masks being too conservative.Matthias Braun1-1/+1
When calculating the lanemask of a register class we have to include the masks of subregisters supported by any of the class members, not just the ones supported by all class members. This fixes problems when coalescing towards a subclass with additional subregisters available. The attached testcase works fine as is, but does crash if you enable subregister liveness on x86 without this change applied. llvm-svn: 232652
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