aboutsummaryrefslogtreecommitdiff
path: root/llvm/test/CodeGen
AgeCommit message (Expand)AuthorFilesLines
2025-12-01[AMDGPU] Allow hazard checks for WMMA co-exec (#168805)Stanislav Mekhanoshin1-0/+56
2025-12-01Revert "[BPF] Allow libcalls behind a feature gate (#168442)" (#169733)Lucas Ste4-41/+4
2025-12-01[X86] combineConcatVectorOps - add handling to concat ISD::FROUND/FFLOOR intr...Simon Pilgrim2-137/+146
2025-12-01[SPIRV] Add legalization for long vectors (#169665)Steven Perron2-0/+202
2025-12-01[X86] Add test coverage for the concatenation of ISD::FROUND intrinsics (#170...Simon Pilgrim1-0/+425
2025-12-01[X86] Add test coverage for the concatenation of ISD::FFLOOR intrinsics (#170...Simon Pilgrim1-0/+178
2025-12-01[RISCV] Rename SFB Base Feature (#169607)Sam Elliott14-28/+28
2025-12-01[AArch64][GlobalISel] Add GISel coverage for i32 lround and lrint. NFCDavid Green4-68/+151
2025-12-01[X86] combineConcatVectorOps - add handling to concat fp rounding intrinsics ...Simon Pilgrim6-216/+324
2025-12-01[X86] Add test coverage for the concatenation of vXf64 sqrt intrinsics (#170158)Simon Pilgrim1-0/+84
2025-12-01[X86] combineConcatVectorOps - add handling to concat RCPPS/RSQRTPS intrinsic...Simon Pilgrim2-24/+24
2025-12-01[X86] combineConcatVectorOps - add handling to concat sqrt intrinsics togethe...Simon Pilgrim1-12/+11
2025-12-01[LLVM][CodeGen] Remove failure cases when widening EXTRACT/INSERT_SUBVECTOR. ...Paul Walker2-107/+425
2025-12-01[X86] Add tests showing failure to concat fp rounding intrinsics together. (#...Simon Pilgrim6-0/+1019
2025-12-01[WebAssembly] Optimize away mask of 63 for shl ( zext (and i32 63))) (#152397)Jasmine Tang1-0/+15
2025-12-01[X86] Add tests showing failure to concat RCPPS + RSQRTPS intrinsics together...Simon Pilgrim2-0/+130
2025-12-01[X86] Add tests showing failure to concat sqrt intrinsics together. (#170096)Simon Pilgrim1-0/+91
2025-12-01[RISCV] Remove the duplicate for RV32/RV64 in zicond-fp-select-zfinx.ll. NFC.Jim Lin1-192/+97
2025-12-01[AArch64][SME] Support saving/restoring ZT0 in the MachineSMEABIPass (#166362)Benjamin Maxwell3-76/+305
2025-12-01[RISCV][llvm] Correct shamt in P extension EXTRACT_VECTOR_ELT lowering (#169823)Brandon Wu2-0/+44
2025-11-30[SPIRV] Added support for extension SPV_ALTERA_arbitrary_precision_fixed_poin...Aadesh Premkumar9-21/+275
2025-12-01[RISCV][ISelLowering] Use Zicond for FP selects on Zfinx/Zdinx (#169299)fennecJ1-0/+798
2025-11-30[DAG] getCarry - always succeed if we encounter a i1 type during trunc/ext pe...Simon Pilgrim1-12/+3
2025-11-30[ARM] Introduce intrinsics for MVE fma under strict-fp. (#169771)David Green1-12/+112
2025-11-29[X86] combineConcatVectorOps - add handling for vXi1 concat(logicop(),logicop...Simon Pilgrim1-30/+14
2025-11-29[SPARC] Properly handle CC for long double on sparc32 (#162226)Koakuma3-114/+191
2025-11-29Revert "[RegAlloc] Relax the split constrain on MBB prolog" (#169990)theRonShark8-3461/+3237
2025-11-29[RISCV] Intrinsic Support for XCVelw (#129168)Qihan Cai1-0/+27
2025-11-29[RegAlloc] Relax the split constrain on MBB prolog (#168259)Luo Yuanke8-3237/+3461
2025-11-28[AArch64] Guard for 128bit vectors in mull combine. (#169839)David Green1-0/+28
2025-11-28[AArch64][SVE] Add basic support for `@llvm.masked.compressstore` (#168350)Benjamin Maxwell2-0/+297
2025-11-28[AArch64][GlobalISel] Improve lowering of vector fp16 fptrunc (#163398)Ryan Cowan5-184/+66
2025-11-28[LoongArch] Make rotl/rotr custom for lsx/lasx (#161154)Zhaoxin Yang2-142/+70
2025-11-28[AMX][NFC] Organize tilerow (#168193)Mahesh-Attarde2-4/+4
2025-11-27[NFC] [DirectX] Make DirectX codegen test `CBufferAccess/gep-ce-two-uses.ll` ...Deric C.1-5/+8
2025-11-27[NFC] [DirectX] Update DirectX codegen test `CBufferAccess/gep-ce-two-uses.ll...Deric C.1-0/+16
2025-11-27[AArch64] Use SVE for fixed-length bf16 operations with +sve-b16b16 (#169329)Benjamin Maxwell2-85/+954
2025-11-27[AArch64] Use umin for x != 0 when +cssc is enabled (#169159)clf2-2/+338
2025-11-27Revert "[ShrinkWrap] Modify shrink wrapping to accommodate functions terminat...Alex Bradbury1-179/+0
2025-11-27[AArch64] recognise zip1/zip2 with flipped operands (#167235)Philip Ginsbach-Chen6-187/+145
2025-11-27[AMDGPU] Remove odd syntax in some RUN lines. NFC. (#169831)Jay Foad3-8/+8
2025-11-27[SPIRV][AMD] Disable SPV_KHR_float_control2 for AMD flavored SPIRV (#169659)Juan Manuel Martinez Caamaño1-0/+22
2025-11-27[X86] rem-vector-lkk.ll - improve CPU coverage to cover all x86-64 levels (#1...Simon Pilgrim2-206/+526
2025-11-27[SystemZ] Serialize ada entry flags (#169395)Kai Nacke1-0/+17
2025-11-27[X86] optimize ssse3 horizontal saturating add/sub (#169591)Folkert de Vries1-0/+101
2025-11-27[ShrinkWrap] Modify shrink wrapping to accommodate functions terminated by no...Nathan Corbyn1-0/+179
2025-11-27[ARM] Remove IR from mve vpt mir tests. NFCDavid Green10-230/+23
2025-11-27[LoongArch][NFC] Pre-commit tests for vector rotl/rotr (#161115)Zhaoxin Yang2-0/+566
2025-11-26[ReplaceConstant] Don't create instructions for the same constant multiple ti...Shilei Tian3-58/+124
2025-11-26[SystemZ] Emit optional argument area length field (#169679)Kai Nacke1-0/+66
generated by cgit v1.2.3 (git 2.39.1) at 2026-05-18 11:03:31 +0000