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2026-01-05[AMDGPU] Add new llvm.amdgcn.wave.shuffle intrinsic (#167372)saxlungs1-0/+226
2026-01-05[ISel] Introduce llvm.clmul intrinsic (#168731)Ramkumar Ramachandra3-0/+13616
2026-01-05Honor alignment for HVX masked loads/stores (incl. loops) (#174419)Fateme Hosseini2-0/+90
2026-01-05[AArch64] Make ISD::CTLS Legal for i32 and i64. (#174367)Craig Topper1-3/+42
2026-01-05[X86][NewPM] Port x86-fast-tile-config to NewPM (#174446)Aiden Grossman1-1/+2
2026-01-05[X86] combineConcatVectorOps - add missing X86ISD::CMPM handling (#174420)Simon Pilgrim1-5/+6
2026-01-05[AMDGPU] Generate more efficient code to avoid shift64 hazard (#171871)LU-JOHN1-25/+10
2026-01-05[X86] Add tests showing failure to concat comparisons due to the delayed expa...Simon Pilgrim1-0/+71
2026-01-05[AMDGPU] Remove UTC line from file that does not use itAiden Grossman1-1/+0
2026-01-05[X86] combineConcatVectorOps - concat fma chains which share concatenated ope...Simon Pilgrim1-23/+33
2026-01-05[X86] combineConcatVectorOps - check for an existing operands concatenation (...Simon Pilgrim1-13/+13
2026-01-05[X86] Add test showing failure to make use of existing concatenated operands ...Simon Pilgrim1-2/+67
2026-01-05[llvm][RISCV] Support fma codegen for zvfbfa (#172949)Brandon Wu10-505/+5311
2026-01-04[RISCV][SelectionDAG] Add a ISD::CTLS node for count leading redundant sign b...Craig Topper2-0/+244
2026-01-04[X86][NewPM] Port x86-fast-pre-tile-config (#174323)Aiden Grossman7-7/+13
2026-01-04[X86] LowerMINMAX - use valuetracking to attempt to find a smaller type that ...Simon Pilgrim5-170/+64
2026-01-04[X86] LowerShift - if a vXi8 shift amount is small enough skip additional inc...Simon Pilgrim1-346/+135
2026-01-04[SDAG] Avoid crash when creating debug fragments for scalable vectors (#165233)Benjamin Maxwell1-0/+48
2026-01-04[X86][NewPM] Port x86-domain-reassignment (#174321)Aiden Grossman2-0/+2
2026-01-04[X86][NewPM] Port x86-compress-evex (#174312)Aiden Grossman1-0/+1
2026-01-03[LLVM] Make crashing tests with not use --crashAiden Grossman5-5/+5
2026-01-03[RISCV] Add +zbb to scalar P extension tests. NFCCraig Topper2-6/+5
2026-01-04Revert "[AMDGPU] add clamp immediate operand to WMMA iu8 intrinsic (#171069)"...Shilei Tian5-31/+31
2026-01-04[IR] Reland Optimize PHINode::removeIncomingValue() and PHINode::removeIncomi...Mingjie Xu1-1/+1
2026-01-03[RISCV] Support i32 SSHLAT for rv32ip. (#173687)Craig Topper1-0/+34
2026-01-03[X86][NewPM] Port x86-avoid-sfb to the New Pass Manager (#174166)Aiden Grossman5-6/+12
2026-01-03AMDGPU: Remove dead check prefixes from test (#174280)Matt Arsenault1-60/+0
2026-01-03AMDGPU: Remove some unnecessary callsite attributes from tests (#174270)Matt Arsenault6-22/+22
2026-01-03[X86] combinePTESTCC - always prefer TESTPS/D to PTEST on AVX (#174097)Simon Pilgrim1-19/+7
2026-01-03[X86][AMX] Move Stride close to its use (#174095)Phoebe Wang2-1/+40
2026-01-02[X86] Add basic test coverage for #174169 (#174226)Simon Pilgrim4-0/+1259
2026-01-02[AMDGPU] Add `nocreateundeforpoison` annotations (#166450)Krzysztof Drewniak11-30/+40
2026-01-02[AArch64][GlobalISel] Add extra csel test coverage. NFCDavid Green2-158/+361
2026-01-02[AArch64] Combine (not (shift X, C)) into MVN (#174180)Piotr Fusik2-10/+92
2026-01-02[NVPTX] Add missing preconditions to tensormap replace tests (#174190)Srinivasa Ravi2-2/+2
2026-01-02[AArch64][GlobalISel] Add disjoint to the G_OR when lowering G_ROTR/L (#172317)David Green6-358/+196
2026-01-01[X86][NewPM] Port x86-cf-opt to the New Pass Manager (#174168)Aiden Grossman2-0/+2
2026-01-02[AMDGPU][NewPM] Format llc-pipeline-npm.ll better (#174161)Aiden Grossman1-7/+421
2026-01-02[RISCV][GISel] Support select vsetvli intrinsics (#174076)Jianjian Guan1-0/+153
2026-01-01[NVPTX] Add proper precondition in tensormap_replace_sm_103a test (#174144)Walter Lee1-1/+1
2026-01-01[AMDGPU][NPM] Disable few non useful passes (#172796)Vikram Hegde1-3/+3
2026-01-01[NPM] Update OptimizedRegAlloc and MachineLateOptimization pipelines (#172795)Vikram Hegde1-2/+2
2026-01-01[NVPTX] Add intrinsics and codegen for tensormap.replace (#172458)Srinivasa Ravi4-0/+368
2025-12-31[X86][NewPM] Port X86FixupLEAs to NPMAiden Grossman3-3/+8
2025-12-31[X86][NewPM] Port X86FlagsCopyLowering to NPMAiden Grossman3-0/+5
2025-12-31[X86][AMX-AVX512] Add *i intrinsics for immediate variants (#173545)Phoebe Wang1-6/+6
2025-12-31[CodeGen][NPM] Remove "LowerConstantIntrinsicsPass" from the pipeline (#172794)Vikram Hegde1-3/+3
2025-12-31[X86] Add additional test coverage for #162812 (#174080)Simon Pilgrim1-5/+755
2025-12-31[RISCV] Convert ORI with SingleBitSetMaskImm12 to BSETI when Xqcibm is enable...Sudharsan Veeravalli1-0/+57
2025-12-31[AArch64] - Allow for aggressive unrolling, with non-zero LoopMicroOpBufferS...Pawan Nirpal1-0/+152
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