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2012-06-29In the initial exec mode we always do a load to find the address of a variable.Rafael Espindola1-4/+4
Before this patch in pic 32 bit code we would add the global base register and not load from that address. This is a really old bug, but before the introduction of the tls attributes we would never select initial exec for pic code. llvm-svn: 159409
2012-06-29misched: avoid scheduling instructions that can't be dispatched.Andrew Trick1-6/+29
llvm-svn: 159408
2012-06-29misched: count micro-ops toward the issue limit.Andrew Trick1-10/+19
llvm-svn: 159407
2012-06-29Make NumMicroOps a variable in the subtarget's instruction itinerary.Andrew Trick5-49/+64
The TargetInstrInfo::getNumMicroOps API does not change, but soon it will be used by MachineScheduler. Now each subtarget can specify the number of micro-ops per itinerary class. For ARM, this is currently always dynamic (-1), because it is used for load/store multiple which depends on the number of register operands. Zero is now a valid number of micro-ops. This can be used for nop pseudo-instructions or instructions that the hardware can squash during dispatch. llvm-svn: 159406
2012-06-29X86: add more GATHER intrinsics in LLVMManman Ren4-23/+60
Corrected type for index of llvm.x86.avx2.gather.d.pd.256 from 256-bit to 128-bit. Corrected types for src|dst|mask of llvm.x86.avx2.gather.q.ps.256 from 256-bit to 128-bit. Support the following intrinsics: llvm.x86.avx2.gather.d.q, llvm.x86.avx2.gather.q.q llvm.x86.avx2.gather.d.q.256, llvm.x86.avx2.gather.q.q.256 llvm.x86.avx2.gather.d.d, llvm.x86.avx2.gather.q.d llvm.x86.avx2.gather.d.d.256, llvm.x86.avx2.gather.q.d.256 llvm-svn: 159402
2012-06-28If the step value is a constant zero, the loop isn't going to terminate. FixesNick Lewycky1-1/+1
the assert reported in PR13228! llvm-svn: 159393
2012-06-28make the verifier accept @llvm.donothing as the only intrinsic that can be ↵Nuno Lopes1-2/+4
invoked While at it, merge 2 tests and FileCheckize them llvm-svn: 159388
2012-06-28make simplifyCFG erase invokes to readonly/readnone functionsNuno Lopes1-6/+7
llvm-svn: 159385
2012-06-28make instcombine produce calls to llvm.donothing instead of a random intrinsicNuno Lopes1-7/+4
llvm-svn: 159384
2012-06-28add a new @llvm.donothing intrinsic that, well, does nothing, and teach ↵Nuno Lopes1-1/+8
CodeGen to ignore calls to it llvm-svn: 159383
2012-06-28'Promote' vector [su]int_to_fp should widen elements.Jim Grosbach1-3/+54
Teach vector legalization how to honor Promote for int to float conversions. The code checking whether to promote the operation knew to look at the operand, but the actual promotion code didn't. This fixes that. The operand is promoted up via [zs]ext. rdar://11762659 llvm-svn: 159378
2012-06-28Changed the formatting sequence of a curly brace to Jack Carter1-2/+2
the comment per code review feedback. llvm-svn: 159376
2012-06-28Remove layering violation #include.Bill Wendling1-1/+0
llvm-svn: 159372
2012-06-28Enable automatic GCC<->LLVM intrinsic translation for mips.Benjamin Kramer1-1/+6
llvm-svn: 159367
2012-06-28MemoryBuiltins:Nuno Lopes1-14/+37
- recognize C++ new(std::nothrow) friends - ignore ExtractElement and ExtractValue instructions in size/offset analysis (all easy cases are probably folded away before we get here) - also recognize realloc as noalias llvm-svn: 159356
2012-06-28make LazyValueInfo analyze the default case of switch statements (we know ↵Nuno Lopes1-16/+15
that in the default branch the value cannot be any of the switch cases) llvm-svn: 159353
2012-06-28add ConstantRange::difference (to perform set difference/relative complement)Nuno Lopes1-0/+6
llvm-svn: 159352
2012-06-28Devirtualize DIScope and subclasses.Benjamin Kramer1-26/+0
Nothing in here makes use of the virtuality. llvm-svn: 159349
2012-06-28[asan] set a hard limit on the number of instructions instrumented pear each ↵Kostya Serebryany1-0/+12
BB. This is (hopefully temporary) workaround for PR13225 llvm-svn: 159344
2012-06-28Precompute SCEV pointer analysis prior to instruction fusion in BBVectorize.Hal Finkel1-10/+51
When both a load/store and its address computation are being vectorized, it can happen that the address-computation vectorization destroys SCEV's ability to analyize the relative pointer offsets. As a result (like with the aliasing analysis info), we need to precompute the necessary information prior to instruction fusing. This was found during stress testing (running through the test suite with a very low required chain length); unfortunately, I don't have a small test case. llvm-svn: 159332
2012-06-28Remove a useless check in BBVectorize.Hal Finkel1-5/+0
A shuffle mask will always be a constant, but I did not realize that when I originally wrote the code. llvm-svn: 159331
2012-06-28Allow BBVectorize to form non-2^n-length vectors.Hal Finkel1-132/+532
The original algorithm only used recursive pair fusion of equal-length types. This is now extended to allow pairing of any types that share the same underlying scalar type. Because we would still generally prefer the 2^n-length types, those are formed first. Then a second set of iterations form the non-2^n-length types. Also, a call to SimplifyInstructionsInBlock has been added after each pairing iteration. This takes care of DCE (and a few other things) that make the following iterations execute somewhat faster. For the same reason, some of the simple shuffle-combination cases are now handled internally. There is some additional refactoring work to be done, but I've had many requests for this feature, so additional refactoring will come soon in future commits (as will additional test cases). llvm-svn: 159330
2012-06-28Refactor operation equivalence checking in BBVectorize by extending ↵Hal Finkel2-28/+18
Instruction::isSameOperationAs. Maintaining this kind of checking in different places is dangerous, extending Instruction::isSameOperationAs consolidates this logic into one place. Here I've added an optional flags parameter and two flags that are important for vectorization: CompareIgnoringAlignment and CompareUsingScalarTypes. llvm-svn: 159329
2012-06-28Only print out the tag if it's there.Bill Wendling1-1/+2
llvm-svn: 159328
2012-06-28Don't output an empty string.Bill Wendling1-2/+3
llvm-svn: 159327
2012-06-28The Mips specific inline asm operand modifier 'z' has theJack Carter1-1/+13
following description in the gnu sources: Print $0 if operand is zero otherwise print the op normally. llvm-svn: 159324
2012-06-28make LVI::getEdgeValue() always intersect the constraints of the edge with ↵Nuno Lopes1-36/+53
the range of the block. Previously it was only performing the intersection for a few cases, thus losing precision llvm-svn: 159320
2012-06-28fix a off-by-one bug in intersectWith(), and add a bunch of testsNuno Lopes1-1/+1
llvm-svn: 159319
2012-06-28Use the interface through DIDescriptor to get the tag/version for a debug infoBill Wendling1-9/+11
MDNode. llvm-svn: 159317
2012-06-28Fix cmake failure from moving files around.Bill Wendling2-1/+1
llvm-svn: 159314
2012-06-28Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp andBill Wendling38-103/+101
include/llvm/Analysis/DebugInfo.h to include/llvm/DebugInfo.h. The reasoning is because the DebugInfo module is simply an interface to the debug info MDNodes and has nothing to do with analysis. llvm-svn: 159312
2012-06-27This allows hello world to be compiled for Mips 64 direct object.Jack Carter1-0/+1
It takes advantage of r159299 which introduces relocation support for N64. elf-dump needed to be upgraded to support N64 relocations as well. This passes make check. Jack llvm-svn: 159302
2012-06-27This allows hello world to be compiled for Mips 64 direct object.Jack Carter4-3/+54
It takes advantage of r159299 which introduces relocation support for N64. elf-dump needed to be upgraded to support N64 relocations as well. This passes make check. Jack llvm-svn: 159301
2012-06-27Whitespace.Chad Rosier1-34/+34
llvm-svn: 159300
2012-06-27The ELF relocation record format is different for N64 Jack Carter3-12/+24
which many Mips 64 ABIs use than for O64 which many if not all other target ABIs use. Most architectures have the following 64 bit relocation record format: typedef struct { Elf64_Addr r_offset; /* Address of reference */ Elf64_Xword r_info; /* Symbol index and type of relocation */ } Elf64_Rel; typedef struct { Elf64_Addr r_offset; Elf64_Xword r_info; Elf64_Sxword r_addend; } Elf64_Rela; Whereas N64 has the following format: typedef struct { Elf64_Addr r_offset;/* Address of reference */ Elf64_Word r_sym; /* Symbol index */ Elf64_Byte r_ssym; /* Special symbol */ Elf64_Byte r_type3; /* Relocation type */ Elf64_Byte r_type2; /* Relocation type */ Elf64_Byte r_type; /* Relocation type */ } Elf64_Rel; typedef struct { Elf64_Addr r_offset;/* Address of reference */ Elf64_Word r_sym; /* Symbol index */ Elf64_Byte r_ssym; /* Special symbol */ Elf64_Byte r_type3; /* Relocation type */ Elf64_Byte r_type2; /* Relocation type */ Elf64_Byte r_type; /* Relocation type */ Elf64_Sxword r_addend; } Elf64_Rela; The structure is the same size, but the r_info data element is now 5 separate elements. Besides the content aspects, endian byte reordering will be different for the area with each element being endianized separately. I treat this as generic and continue to pass r_type as an integer masking and unmasking the byte sized N64 values for N64 mode. I've implemented this and it causes no affect on other current targets. This passes make check. Jack llvm-svn: 159299
2012-06-27Revert r159136 due to PR13124.Matt Beaumont-Gay1-11/+0
Original commit message: If a constant or a function has linkonce_odr linkage and unnamed_addr, mark it hidden. Being linkonce_odr guarantees that it is available in every dso that needs it. Being a constant/function with unnamed_addr guarantees that the copies don't have to be merged. llvm-svn: 159272
2012-06-27Some reassociate optimizations create new instructions, which they insert justDuncan Sands1-11/+7
before the expression root. Any existing operators that are changed to use one of them needs to be moved between it and the expression root, and recursively for the operators using that one. When I rewrote RewriteExprTree I accidentally inverted the logic, resulting in the compacting going down from operators to operands rather than up from operands to the operators using them, oops. Fix this, resolving PR12963. llvm-svn: 159265
2012-06-27Teach assembler to handle capitalised operation values for DSB instructionsRichard Barton1-1/+1
llvm-svn: 159259
2012-06-27Prevent ARM Assembler crashing on unrecognised assembly format for DSB ↵Richard Barton1-1/+2
instruction llvm-svn: 159257
2012-06-27Silence uninitialized variable warning in MipsISelDAGToDAG.cpp.Akira Hatanaka1-1/+1
llvm-svn: 159243
2012-06-27Fix bug in computation of stack size in MipsFrameLowering.cpp.Akira Hatanaka2-3/+10
llvm-svn: 159240
2012-06-26Reduce indentation in function. Rearrange some methods. No functionality change.Bill Wendling1-223/+222
llvm-svn: 159239
2012-06-26Revamp how debugging information is emitted for debug info objects.Bill Wendling1-134/+84
It's not necessary for each DI class to have its own copy of `print' and `dump'. Instead, just give DIDescriptor those methods and have it call the appropriate debugging printing routine based on the type of the debug information. llvm-svn: 159237
2012-06-26Add a missing check to avoid dereference null. No sensible test case ↵Evan Cheng1-0/+2
possible. Sorry. rdar://11745134 llvm-svn: 159236
2012-06-26Remove a instcombine transform that (no longer?) makes sense:Evan Cheng1-5/+0
// C - zext(bool) -> bool ? C - 1 : C if (ZExtInst *ZI = dyn_cast<ZExtInst>(Op1)) if (ZI->getSrcTy()->isIntegerTy(1)) return SelectInst::Create(ZI->getOperand(0), SubOne(C), C); This ends up forming sext i1 instructions that codegen to terrible code. e.g. int blah(_Bool x, _Bool y) { return (x - y) + 1; } => movzbl %dil, %eax movzbl %sil, %ecx shll $31, %ecx sarl $31, %ecx leal 1(%rax,%rcx), %eax ret Without the rule, llvm now generates: movzbl %sil, %ecx movzbl %dil, %eax incl %eax subl %ecx, %eax ret It also helps with ARM (and pretty much any target that doesn't have a sext i1 :-). The transformation was done as part of Eli's r75531. He has given the ok to remove it. rdar://11748024 llvm-svn: 159230
2012-06-26Implement getHostCPUName for ARM/linux. This will be used to implement ↵Benjamin Kramer1-0/+55
-march=native in clang. The cpuid registers are only available in privileged mode so we don't have an OS-independent way of implementing this. ARM doesn't provide a list of processor IDs so the list is somewhat incomplete. llvm-svn: 159228
2012-06-26X86: add GATHER intrinsics (AVX2) in LLVMManman Ren7-4/+132
Support the following intrinsics: llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256 llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256 Modified Disassembler to handle VSIB addressing mode. llvm-svn: 159221
2012-06-26Fix ThreadLocalImpl::getInstance for --disable-threads.Argyrios Kyrtzidis1-3/+5
PR13114. llvm-svn: 159210
2012-06-26Allow targets to inject passes before the virtual register rewriter.Jakob Stoklund Olesen1-1/+5
Such passes can be used to tweak the register assignments in a target-dependent way, for example to avoid write-after-write dependencies. llvm-svn: 159209
2012-06-26There are a number of generic inline asm operand modifiers thatJack Carter9-9/+39
up to r158925 were handled as processor specific. Making them generic and putting tests for these modifiers in the CodeGen/Generic directory caused a number of targets to fail. This commit addresses that problem by having the targets call the generic routine for generic modifiers that they don't currently have explicit code for. For now only generic print operands 'c' and 'n' are supported.vi Affected files: test/CodeGen/Generic/asm-large-immediate.ll lib/Target/PowerPC/PPCAsmPrinter.cpp lib/Target/NVPTX/NVPTXAsmPrinter.cpp lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/XCore/XCoreAsmPrinter.cpp lib/Target/X86/X86AsmPrinter.cpp lib/Target/Hexagon/HexagonAsmPrinter.cpp lib/Target/CellSPU/SPUAsmPrinter.cpp lib/Target/Sparc/SparcAsmPrinter.cpp lib/Target/MBlaze/MBlazeAsmPrinter.cpp lib/Target/Mips/MipsAsmPrinter.cpp MSP430 isn't represented because it did not even run with the long existing 'c' modifier and it was not apparent what needs to be done to get it inline asm ready. Contributer: Jack Carter llvm-svn: 159203
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