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2011-04-01Avoid de-referencing pass beginning of a basic block. No small test case ↵Evan Cheng1-18/+21
possible. rdar://9216009 llvm-svn: 128743
2011-04-01Remove redundant code. There are assignments to variables Base and Offset ↵Akira Hatanaka1-5/+0
right after the code that is removed. llvm-svn: 128742
2011-04-01Simplifies logic for printing target flags.Akira Hatanaka3-34/+29
llvm-svn: 128741
2011-04-01When the architecture is explicitly armv6 or thumbv6, we need to mark the ↵Owen Anderson1-9/+15
object file appropriately. llvm-svn: 128739
2011-04-01LDRD/STRD instructions should print both Rt and Rt2 in the asm string.Jim Grosbach1-10/+5
llvm-svn: 128736
2011-04-01Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we ↵Johnny Chen1-0/+8
should reject the instruction as invalid. llvm-svn: 128734
2011-04-01Fix build.Benjamin Kramer1-1/+2
llvm-svn: 128733
2011-04-01InstCombine: Turn icmp + sext into bitwise/integer ops when the input has ↵Benjamin Kramer1-0/+50
only one unknown bit. int test1(unsigned x) { return (x&8) ? 0 : -1; } int test3(unsigned x) { return (x&8) ? -1 : 0; } before (x86_64): _test1: andl $8, %edi cmpl $1, %edi sbbl %eax, %eax ret _test3: andl $8, %edi cmpl $1, %edi sbbl %eax, %eax notl %eax ret after: _test1: shrl $3, %edi andl $1, %edi leal -1(%rdi), %eax ret _test3: shll $28, %edi movl %edi, %eax sarl $31, %eax ret llvm-svn: 128732
2011-04-01InstCombine: Move (sext icmp) transforms into their own method. No intended ↵Benjamin Kramer2-37/+43
functionality change. llvm-svn: 128731
2011-04-01Add comments.Evan Cheng1-2/+4
llvm-svn: 128730
2011-04-01Assign node order numbers to results of call instruction lowering. This ↵Evan Cheng1-4/+8
should improve src line debug info when sdisel is used. rdar://9199118 llvm-svn: 128728
2011-04-01Modifies MipsAsmPrinter::isBlockOnlyReachableByFallthrough so that it ↵Akira Hatanaka1-1/+26
handles delay slots correctly. llvm-svn: 128724
2011-04-01Fix LDRi12 immediate operand, which was changed to be the second operand in ↵Johnny Chen1-3/+4
$addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm). rdar://problem/9219356 llvm-svn: 128722
2011-04-01Add code for analyzing FP branches. Clean up branch Analysis functions.Akira Hatanaka2-223/+138
llvm-svn: 128718
2011-04-01Initialize HasVMLxForwarding.Benjamin Kramer1-0/+1
llvm-svn: 128709
2011-04-01Various Instructions' resizeOperands() methods are only used to grow theJay Foad1-54/+16
list of operands. Simplify and rename them accordingly. llvm-svn: 128708
2011-04-01While testing dragonegg I noticed that isCastable and getCastOpcodeDuncan Sands1-4/+12
had gotten out of sync: isCastable didn't think it was possible to cast the x86_mmx type to anything, while it did think it possible to cast an i64 to x86_mmx. llvm-svn: 128705
2011-04-01Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs.Evan Cheng3-19/+164
rdar://8911343 llvm-svn: 128696
2011-04-01Remove unused variablesMatt Beaumont-Gay1-3/+1
llvm-svn: 128692
2011-03-31Apply again changes to support ARM memory asm parsing. I removedBruno Cardoso Lopes9-76/+329
all LDR/STR changes and left them to a future patch. Passing all checks now. - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and fix the encoding wherever is possible. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128689
2011-03-31The basic register allocator must also use the inline spiller.Jakob Stoklund Olesen1-1/+1
It is using a trivial rewriter that doesn't know how to insert spill code requested by the standard spiller. llvm-svn: 128688
2011-03-31Provide a legal pointer register class when targeting thumb1.Jakob Stoklund Olesen2-0/+7
The LocalStackSlotAllocation pass was creating illegal registers. llvm-svn: 128687
2011-03-31Instcombile optimization: extractelement(cast) -> cast(extractelement)Nadav Rotem1-1/+9
llvm-svn: 128683
2011-03-31InstCombine: APFloat can't perform arithmetic on PPC double doubles, don't ↵Benjamin Kramer1-2/+4
even try. Thanks Eli! llvm-svn: 128676
2011-03-31Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplierEvan Cheng3-3/+53
accumulator forwarding: vadd d3, d0, d1 vmul d3, d3, d2 => vmul d3, d0, d2 vmla d3, d1, d2 llvm-svn: 128665
2011-03-31Fix single word and unsigned byte data transfer instruction encodings so thatJohnny Chen1-0/+2
Inst{4} = 0. rdar://problem/9213022 llvm-svn: 128662
2011-03-31Added support for FP conditional move instructions and fixed bugs in ↵Akira Hatanaka7-285/+377
handling of FP comparisons. llvm-svn: 128650
2011-03-31Don't completely eliminate identity copies that also modify super register ↵Jakob Stoklund Olesen1-6/+12
liveness. Turn them into noop KILL instructions instead. This lets the scavenger know when super-registers are killed and defined. llvm-svn: 128645
2011-03-31Add BLXi to the instruction table for disassembly purpose.Johnny Chen2-2/+23
A8.6.23 BLX (immediate) rdar://problem/9212921 llvm-svn: 128644
2011-03-31Allow kill flags on two-address instructions. They are harmless.Jakob Stoklund Olesen1-6/+2
llvm-svn: 128643
2011-03-31Mark all uses as <undef> when joining a copy.Jakob Stoklund Olesen3-8/+20
This way, shrinkToUses() will ignore the instruction that is about to be deleted, and we avoid leaving invalid live ranges that SplitKit doesn't like. Fix a misunderstanding in MachineVerifier about <def,undef> operands. The <undef> flag is valid on def operands where it has the same meaning as <undef> on a use operand. It only applies to sub-register defines which also read the full register. llvm-svn: 128642
2011-03-31Remove dead code.Devang Patel1-5/+1
llvm-svn: 128639
2011-03-31Revert r128632 again, until I figure out what break the testsBruno Cardoso Lopes9-322/+87
llvm-svn: 128635
2011-03-31Fix bug found by valgrind.Jakob Stoklund Olesen1-1/+1
llvm-svn: 128634
2011-03-31Add XCore intrinsics for initializing / starting / synchronizing threads.Richard Osborne1-6/+39
llvm-svn: 128633
2011-03-31Reapply r128585 without generating a lib depedency cycle. An updated log:Bruno Cardoso Lopes9-87/+322
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible. - Move all instructions which use am2offset without a pattern to use addrmode2. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128632
2011-03-31lib/CodeGen/LiveIntervalAnalysis.cpp: [PR9590] Don't use ↵NAKAMURA Takumi1-1/+3
std::pow(float,float) here. We don't expect the real "powf()" on some hosts (and powf() would be available on other hosts). For consistency, std::pow(double,double) may be called instead. Or, precision issue might attack us, to see unstable regalloc and stack coloring. llvm-svn: 128629
2011-03-31InstCombine: Fix transform to use the swapped predicate.Benjamin Kramer1-2/+2
Thanks Frits! llvm-svn: 128628
2011-03-31InstCombine: fold fcmp (fneg x), (fneg y) -> fcmp x, yBenjamin Kramer1-0/+5
llvm-svn: 128627
2011-03-31InstCombine: fold fcmp pred (fneg x), C -> fcmp swap(pred) x, -CBenjamin Kramer1-0/+8
llvm-svn: 128626
2011-03-31InstCombine: Shrink "fcmp (fpext x), C" to "fcmp x, C" if C can be ↵Benjamin Kramer1-0/+34
losslessly converted to the type of x. Fixes PR9592. llvm-svn: 128625
2011-03-31InstCombine: fold fcmp (fpext x), (fpext y) -> fcmp x, y.Benjamin Kramer1-0/+7
llvm-svn: 128624
2011-03-31Pick a conservative register class when creating a small live range for remat.Jakob Stoklund Olesen1-1/+1
The rematerialized instruction may require a more constrained register class than the register being spilled. In the test case, the spilled register has been inflated to the DPR register class, but we are rematerializing a load of the ssub_0 sub-register which only exists for DPR_VFP2 registers. The register class is reinflated after spilling, so the conservative choice is only temporary. llvm-svn: 128610
2011-03-31Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and"Matt Beaumont-Gay7-285/+66
This revision introduced a dependency cycle, as nlewycky mentioned by email. llvm-svn: 128597
2011-03-30Somehow we managed to forget to encode the lane index for a large swathe of ↵Owen Anderson2-21/+70
NEON instructions. With this fix, the entire test-suite passes with the Thumb integrated assembler. llvm-svn: 128587
2011-03-30Don't try to create zero-sized stack objects.Evan Cheng2-4/+6
llvm-svn: 128586
2011-03-30- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT andBruno Cardoso Lopes7-66/+285
{STR,LDC}{2}_PRE. - Fixed the encoding in some places. - Some of those instructions were using am2offset and now use addrmode2. Codegen isn't affected, instructions which use SelectAddrMode2Offset were not touched. - Teach printAddrMode2Operand to check by the addressing mode which index mode to print. - This is a work in progress, more work to come. The idea is to change places which use am2offset to use addrmode2 instead, as to unify assembly parser. - Add testcases for assembly parser llvm-svn: 128585
2011-03-30Add a ARM-specific SD node for VBSL so that forms with a constant first operandCameron Zwarich4-9/+82
can be recognized. This fixes <rdar://problem/9183078>. llvm-svn: 128584
2011-03-30* The DSE code that tested for overlapping needed to take into account the factBill Wendling1-1/+3
that one of the numbers is signed while the other is unsigned. This could lead to a wrong result when the signed was promoted to an unsigned int. * Add the data layout line to the testcase so that it will test the appropriate thing. Patch by David Terei! llvm-svn: 128577
2011-03-30fixed typoAkira Hatanaka1-2/+2
llvm-svn: 128574
generated by cgit v1.1 at 2025-10-17 22:35:43 +0000