aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib
AgeCommit message (Expand)AuthorFilesLines
2026-01-13[CodeGen] Enhance createFrom for sub-reg aware cloningusers/cdevadas/enhance-createFrom-functionChristudasan Devadasan1-1/+9
2026-01-13suggestions incorporated.users/cdevadas/make-AMDGPURewriteAGPRCopyMFMA-subreg-reload-awareChristudasan Devadasan1-2/+2
2026-01-13[AMDGPU] Make AMDGPURewriteAGPRCopyMFMA aware of subreg reloadChristudasan Devadasan2-1/+51
2026-01-13fixed a comment.users/cdevadas/make-getNumSubRegsForSpillOp-member-functionChristudasan Devadasan1-1/+1
2026-01-13moved the implementation to SIInstrInfo.Christudasan Devadasan4-151/+150
2026-01-13[AMDGPU] Make getNumSubRegsForSpillOp externally available (NFC).Christudasan Devadasan2-3/+5
2026-01-13incorporated review comments.users/cdevadas/add-spill-offset-to-sgpr-spill-pseudosChristudasan Devadasan1-3/+3
2026-01-13[AMDGPU] Introduce Offset field in SGPR spill PseudosChristudasan Devadasan3-6/+8
2026-01-13[CodeGen][InlineSpiller] Add SubReg argument to loadRegFromStackSlot for subr...Christudasan Devadasan47-50/+57
2026-01-12[RISCV] Add the missing SEW search table field to vector FMA instructions (#1...Min-Yih Hsu1-1/+1
2026-01-12[profcheck] Fix encoding of 0 loopEstimatedTrip count (#174896)Mircea Trofin1-1/+4
2026-01-13[AMDGPU]Add specific instruction feature for multicast load (#175503)Shoreshen4-3/+17
2026-01-13[RISCV] Adjust base cost for Xqcilo loads/stores in RISCVMakeCompressible (#1...Sudharsan Veeravalli1-7/+38
2026-01-13[RISCV] Use LD_RV32/SD_RV32 for spills and reloads when Zilsd is enabled (#15...Sudharsan Veeravalli1-6/+18
2026-01-12[llvm][RISCV] Suppress unused `IsMulH` warning. (#175653)Chenguang Wang1-2/+3
2026-01-12[X86][NewPM] Port x86-pre-tile-config (#175649)Aiden Grossman4-23/+57
2026-01-12[VPlan] Merge Select with previous cases in ::computeCost (NFC).Florian Hahn1-1/+0
2026-01-12[X86][NewPM] Port x86-tile-config (#175647)Aiden Grossman4-18/+45
2026-01-12[AMDGPU] Add DS loop waitcnt optimization for GFX12+ (#172728)hidekisaito1-61/+164
2026-01-12[SelectionDAGISel] Remove unused opcodes. NFC (#175621)Craig Topper1-16/+12
2026-01-12[IR][InstCombine] Fix O(n^2) complexity in SliceUpIllegalIntegerPHI (#175468)Kirill Pertsev2-6/+4
2026-01-12[X86][NewPM] Port x86-fixup-vector-constants (#175622)Aiden Grossman4-20/+49
2026-01-12[VPlan] Cache other type for VPWidenRecipe with Select opcode (NFC).Florian Hahn1-2/+8
2026-01-12[X86][NewPM] Port x86-suppress-apx-for-relocation (#175634)Aiden Grossman4-14/+36
2026-01-12[VectorCombine] foldPermuteOfIntrinsic - support multiple uses of shuffled op...Julian Pokrovsky1-2/+9
2026-01-12[NFC][LLVM] Adopt ListSeparator/interleaved in more places (#172909)Rahul Joshi14-135/+64
2026-01-12[X86][NewPM] Port x86-lower-tile-copy (#175625)Aiden Grossman4-14/+32
2026-01-12[X86][NewPM] Port x86-fixup-setcc (#175609)Aiden Grossman4-21/+33
2026-01-12[VPlan] Check for store group once in VPInterleaveBase() (NFC)Florian Hahn1-9/+10
2026-01-12[AMDGPU]: Rewrite mbcnt_lo/mbcnt_hi to work item ID where applicable (#160496)Teja Alaghari1-0/+116
2026-01-12[DirectX] Update DXILValueEnumerator for the new SwitchInst format (#174672)Deric C.1-0/+8
2026-01-12[NVPTX] Validate user-specified PTX version against SM version (#174834)Justin Fargnoli3-61/+108
2026-01-12[InstCombine] Fix i1 ssub.sat compare folding (#173742)Justin Lebar2-2/+13
2026-01-12[RISCV] Add isel patterns for ANDN/ORN/XNOR with P+Zbb. (#175384)Craig Topper1-0/+15
2026-01-12[Transforms][NFC] Remove unused include in LoopUtils (#175601)Alexis Engelke2-0/+2
2026-01-12InstCombine: Handle rounding intrinsics in SimplifyDemandedFPClass (#174842)Matt Arsenault3-20/+98
2026-01-12[IVDesc] Fix off-by-one error in FindFirstIV ranges (#174441)Ramkumar Ramachandra1-11/+6
2026-01-12[llvm][RISCV] Support rounding mulh for P extension codegen (#171593)Brandon Wu2-13/+63
2026-01-12[NFC][LLVM][AArch64] Simplify `checkPartialMappingIdx` (#173050)Rahul Joshi1-6/+1
2026-01-12[RISCV] Detect QC_E_ADDAI and fold in RISCVMergeBaseOffset (#175496)Sudharsan Veeravalli1-1/+2
2026-01-12[Support][NFC] Make unicode tables constant (#175573)Alexis Engelke2-7/+7
2026-01-12InstCombine: SimplifyDemandedFPClass multiple use support for select (#175548)Matt Arsenault1-1/+27
2026-01-12[ISel] Implement operand widening for VECTOR_FIND_LAST_ACTIVE. (#174389)Florian Hahn2-0/+24
2026-01-12[JITLink] Add GOT indirection optimization for SystemZ (#171919)anoopkg62-2/+38
2026-01-12[AArch64] Define cost of i16->i32 udot/sdot instructions (#174102)Sander de Smalen1-0/+5
2026-01-12[X86][NewPM] Port x86-fixup-inst-tuning (#175576)Aiden Grossman4-18/+50
2026-01-12ValueTracking: Fix handling of fadd with mixed denormal modes (#175454)Matt Arsenault1-1/+4
2026-01-12[SPIRV] Deduce result type for `G_SEXT` and `G_ZEXT` (#175401)Alex Voicu1-0/+2
2026-01-13[VPlan] Give VPInstruction::ExplicitVectorLength name. NFC (#175493)Luke Lau1-1/+1
2026-01-12[AArch64] Add support for range prefetch intrinsic (#170490)Kerry McLaughlin5-0/+50
generated by cgit v1.2.3 (git 2.39.1) at 2026-05-21 19:05:15 +0000