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2025-12-01[rtsan] Handle attributed IR function declarations (#169577)davidtrevelyan1-0/+3
2025-12-01[ProfData] Improve efficiency of reader (#169730)Max1-0/+6
2025-12-01[AMDGPU] Allow hazard checks for WMMA co-exec (#168805)Stanislav Mekhanoshin1-0/+6
2025-12-01Revert "[BPF] Allow libcalls behind a feature gate (#168442)" (#169733)Lucas Ste5-38/+3
2025-12-01[AMDGPU] Refactor hazard recognizer for VALU-pipeline hazards. NFCI. (#168801)Stanislav Mekhanoshin2-39/+55
2025-12-01Fix __apple_XXX iterator that iterates over all entries. (#157538)Greg Clayton1-6/+18
2025-12-01[X86] combineConcatVectorOps - add handling to concat ISD::FROUND/FFLOOR intr...Simon Pilgrim1-0/+2
2025-12-01[VPlan] Improve code in VPInstruction::generate (NFC) (#169470)Ramkumar Ramachandra1-22/+17
2025-12-01[VPlan] Use wide IV if scalar lanes > 0 are used with scalable vectors. (#169...Florian Hahn2-27/+12
2025-12-01[SPIRV] Add legalization for long vectors (#169665)Steven Perron4-24/+242
2025-12-01[AMDGPU][NPM] Preserve analyses in AMDGPURewriteAGPRCopyMFMA for NPM (#170130)Prasoon Mishra1-2/+7
2025-12-01[RISCV] Rename SFB Base Feature (#169607)Sam Elliott8-35/+61
2025-12-01[X86] combineConcatVectorOps - add handling to concat fp rounding intrinsics ...Simon Pilgrim1-0/+16
2025-12-01[WPD] Change Devirt Cutoff to use DebugCounter (#170009)Aiden Grossman1-15/+5
2025-12-01[X86] combineConcatVectorOps - add handling to concat RCPPS/RSQRTPS intrinsic...Simon Pilgrim1-0/+6
2025-12-01[AggressiveInstCombine] Fix memory location for alias analysis (#169953)Yingwei Zheng1-2/+10
2025-12-01[DA] Remove special handling for SCEVAddExpr in GCD MIV (#169927)Ryotaro Kasuga1-18/+0
2025-12-01[DA] Add overflow check when calculating Delta in GCD MIV (#169928)Ryotaro Kasuga1-1/+3
2025-12-01[AArch64] Remove unused references to MVT::f80. (#169545)David Green1-1/+0
2025-12-01[X86] combineConcatVectorOps - add handling to concat sqrt intrinsics togethe...Simon Pilgrim1-0/+6
2025-12-01[LLVM][CodeGen] Remove failure cases when widening EXTRACT/INSERT_SUBVECTOR. ...Paul Walker2-19/+79
2025-12-01[ConstantRange] Allow casting to the same bitwidth. NFC (#170102)Luke Lau2-3/+9
2025-12-01[WebAssembly] Optimize away mask of 63 for shl ( zext (and i32 63))) (#152397)Jasmine Tang2-1/+4
2025-12-01[OMPIRBuilder] CANCEL IF(FALSE) is still a cancellation point (#170095)Tom Eccles1-1/+13
2025-12-01[SelectionDAG] Add SelectionDAG::getTypeSize. NFC (#169764)Luke Lau6-91/+50
2025-12-01[SCCP] Handle llvm.experimental.get.vector.length calls (#169527)Luke Lau1-0/+32
2025-12-01[OMPIRBuilder] re-land cancel barriers patch #164586 (#169931)Tom Eccles1-77/+69
2025-12-01[AArch64][SME] Support saving/restoring ZT0 in the MachineSMEABIPass (#166362)Benjamin Maxwell4-32/+175
2025-12-01[LV] Don't create WidePtrAdd recipes for scalar VFs (#169344)David Sherwood1-1/+2
2025-12-01[InstCombine] Add missing constant check (#170068)Yingwei Zheng1-0/+1
2025-12-01[RISCV][llvm] Correct shamt in P extension EXTRACT_VECTOR_ELT lowering (#169823)Brandon Wu1-1/+1
2025-11-30[SPIRV] Added support for extension SPV_ALTERA_arbitrary_precision_fixed_poin...Aadesh Premkumar9-11/+149
2025-12-01[RISCV][ISelLowering] Use Zicond for FP selects on Zfinx/Zdinx (#169299)fennecJ1-0/+44
2025-11-30[VPlan] Handle canonical IVs in ::isSingleScalar. (NFCI)Florian Hahn1-1/+2
2025-11-30[DAG] getCarry - always succeed if we encounter a i1 type during trunc/ext pe...Simon Pilgrim1-3/+3
2025-11-30[TTI][RISCV] Add cost modelling for intrinsic vp.load.ff (#169890)Shih-Po Hung4-0/+43
2025-11-30[ARM] Introduce intrinsics for MVE fma under strict-fp. (#169771)David Green1-0/+12
2025-11-29Remove unused MCObjectFileInfo::SupportsWeakOmittedEHFrameFangrui Song1-4/+0
2025-11-29[VPlan] Skip cost verification for loops with EVL gather/scatter.Florian Hahn1-11/+23
2025-11-30[SimplifyCFG] Fix `SimplifyCFG` pass to skip folding when both blocks contain...Lucie Choi1-0/+16
2025-11-29[VPlan] Turn IVOp assertion into early exit.Florian Hahn1-3/+4
2025-11-29ARC: Override pseudos with pointersFangrui Song1-0/+2
2025-11-29[X86] combineConcatVectorOps - add handling for vXi1 concat(logicop(),logicop...Simon Pilgrim1-2/+12
2025-11-29[SPARC] Properly handle CC for long double on sparc32 (#162226)Koakuma2-62/+124
2025-11-29Revert "[RegAlloc] Relax the split constrain on MBB prolog" (#169990)theRonShark3-58/+7
2025-11-29[RISCV] Intrinsic Support for XCVelw (#129168)Qihan Cai2-1/+11
2025-11-29[RegAlloc] Relax the split constrain on MBB prolog (#168259)Luo Yuanke3-7/+58
2025-11-28[LV] Vectorize selecting last IV of min/max element. (#141431)Florian Hahn8-18/+271
2025-11-28[MC] [Win64EH] Fix the operator ordering for UOP_SaveFPLRX. NFC.Martin Storsjö1-1/+1
2025-11-28[AMDGPU] Add support for HW_REG_WAVE_SCHED_MODE (#169840)lancesix2-0/+2
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