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path: root/llvm/lib/TargetParser/RISCVISAInfo.cpp
AgeCommit message (Expand)AuthorFilesLines
2026-01-08[RISCV] Add rules for Zca+Zcb+Zcmp+Zcmpt implying Zce. (#175041)Craig Topper1-0/+12
2025-12-20[RISCV] Implement conditional Zca implies C extension rule (#172860)Jerry Zhang Jian1-0/+31
2025-12-18[RISCV] Add Xqci feature flag (#172608)Sudharsan Veeravalli1-4/+4
2025-11-09Remove unused <array> and <list> inclusion (#167116)serge-sans-paille1-1/+0
2025-10-21[RISCV][MC] Introduce XSfvfexp* and XSfvfbfexpa* extensions and their MC supp...Min-Yih Hsu1-0/+6
2025-10-16[RISCV] Make Zalrsc+Zaamo imply A. (#163890)Craig Topper1-1/+1
2025-09-11[RISCV] Make "target-feature +i" explicit (#157835)Gergely Futo1-5/+0
2025-08-20[RISCV] When resolving extension implications, handle the default I/E case af...Owen Anderson1-13/+15
2025-07-27[llvm] Use a range-based for loop instead of {std,llvm}::for_each (NFC) (#150...Kazu Hirata1-10/+9
2025-06-14[RISCV] Use StringRef in a range-based for loop (NFC) (#144243)Kazu Hirata1-2/+1
2025-05-15[RISCV][MC] Add support for Q extension (#139369)Iris Shi1-2/+3
2025-04-27[RISCV] Allow `Zicsr`/`Zifencei` to duplicate with `g` (#136842)Pengcheng Wang1-3/+15
2025-04-22[RISCV] Remove stale comment. NFCCraig Topper1-1/+0
2025-04-21[RISCV] Report error if Zilsd is used on RV64. (#136577)Craig Topper1-0/+3
2025-04-14[RISCV][NFC] Use bitmasks generated by TableGenPengcheng Wang1-31/+11
2025-03-28[RISCV] Add Qualcomm uC Xqciio (External Input Output) extension (#132721)quic_hchandel1-3/+3
2025-03-25[RISCV] Combine 3 bit-manip extensions into `B` (#132858)Tsukasa OI1-2/+2
2025-03-22[RISCV] Implement the implications of C extension (#132259)Jesse Huang1-0/+12
2025-03-22Recommit "[RISCV] Add Qualcomm uC Xqcisync (Sync Delay) extension (#132184)" ...Sudharsan Veeravalli1-4/+4
2025-03-21Revert "[RISCV] Add Qualcomm uC Xqcisync (Sync Delay) extension (#132184)"Kazu Hirata1-4/+4
2025-03-22[RISCV] Add Qualcomm uC Xqcisync (Sync Delay) extension (#132184)quic_hchandel1-4/+4
2025-03-20[RISCV] Add Qualcomm uC Xqcilb (Long Branch) extension (#131996)quic_hchandel1-3/+4
2025-03-19[RISCV] Add Zilsd and Zclsd Extensions (#131094)dong-miao1-0/+8
2025-03-18[RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (#128833)Sudharsan Veeravalli1-1/+1
2025-03-18[RISCV] Add Qualcomm uC Xqcibi (Branch Immediate) extension (#130779)quic_hchandel1-3/+3
2025-03-17[TargetParser] Avoid repeated hash lookups (NFC) (#131555)Kazu Hirata1-2/+3
2025-03-13[RISCV] Add Qualcomm uC Xqcili (load large immediates) extension (#130012)u4f31-3/+3
2025-03-12[RISCV] Add an error that Xqccmp, Xqciac, and Xqcicm are not compatible with ...Craig Topper1-8/+11
2025-03-06[RISCV] Add Qualcomm uC Xqcibm (Bit Manipulation) extension (#129504)users/mariusz-sikora-at-amd/testquic_hchandel1-3/+3
2025-02-26[RISCV] Add Xqccmp 0.1 Assembly Support (#128731)Sam Elliott1-0/+5
2025-02-24[RISCV] Add Qualcomm uC Xqcilia (Large Immediate Arithmetic) extension (#124706)quic_hchandel1-2/+3
2025-01-23[RISCV] Add Qualcomm uC Xqcilo (Large Offset Load Store) extension (#123881)quic_hchandel1-2/+2
2025-01-13[RISCV] Add Qualcomm uC Xqciint (Interrupts) extension (#122256)quic_hchandel1-2/+2
2025-01-07[RISCV] Add Qualcomm uC Xqcicm (Conditional Move) extension (#121752)quic_hchandel1-2/+2
2025-01-03[RISCV] Add Qualcomm uC Xqcicli (Conditional Load Immediate) extension (#121292)Sudharsan Veeravalli1-1/+2
2024-12-29[RISCV] Add Qualcomm uC Xqciac (Load-Store Adress calculation) extension (#12...quic_hchandel1-1/+1
2024-12-14[RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (#119823)Sudharsan Veeravalli1-1/+1
2024-12-12[RISCV] Add Qualcomm uC Xqcics(Conditional Select) extension (#119504)quic_hchandel1-1/+1
2024-12-01[RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (#118113)Sudharsan Veeravalli1-1/+2
2024-11-29[RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store) extension (#117987)Sudharsan Veeravalli1-3/+4
2024-11-28[RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169)Sudharsan Veeravalli1-0/+4
2024-11-12[RISCV] Zabha/Zacas implies Zaamo (#115694)Jim Lin1-5/+0
2024-10-29[RISCV] Remove Zvk* dependency checks from RISCVISAInfo::checkDependency.Craig Topper1-11/+0
2024-10-03[RISCV] Fix RISCVBitPositions typo (#110953)Piyou Chen1-1/+1
2024-08-25[llvm] Prefer StringRef::substr to StringRef::slice (NFC) (#105943)Kazu Hirata1-3/+3
2024-08-19[RISCV] Make extension names lower case in RISCVISAInfo::checkDependency() er...Craig Topper1-4/+4
2024-08-19[RISCV] Add helper functions to exploit similarity of some RISCVISAInfo::chec...Craig Topper1-15/+18
2024-08-19[RISCV] Merge some ISA error reporting together and make some errors more pre...Craig Topper1-32/+23
2024-08-19[RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (#103709)Pengcheng Wang1-2/+7
2024-08-08[RISCV] Support new groupid/bitmask for cpu_model (#101632)Piyou Chen1-29/+34
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