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2024-08-02Revert "[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new ↵Phoebe Wang1-8/+3
instructions" (#101612) Reverts llvm/llvm-project#101452 There are several buildbot failed. Revert first.
2024-08-02[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new ↵Phoebe Wang1-3/+8
instructions (#101452) Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
2024-07-30[X86] Update sub-features of APX for host CPUShengchen Kan1-0/+2
This is a follow-up for https://github.com/llvm/llvm-project/pull/80636
2024-07-24Reland "[compiler-rt][X86] Use functions in cpuid.h instead of inline ↵Aiden Grossman1-80/+18
assembly (#97877)" This reverts commit f1905f064451bf688577976a13000c9c47e58452. This relands commit 19cf8deabe1124831164987f1b9bf2f806c0a875. There were issues with the preprocessor includes that should have excluded MSVC still including clang functions building on windows and using intrin.h. This relanding fixes this behavior by additionally wrapping the uses of __get_cpuid and __get_cpuid_count in _MSC_VER so that clang in MSVC mode, which includes intrin.h, does not have any conflicts.
2024-07-23[PowerPC] Add support for -mcpu=pwr11 / -mtune=pwr11 (#99511)azhan921-0/+7
This PR adds support for -mcpu=pwr11/power11 and -mtune=pwr11/power11 in clang and llvm.
2024-07-23[LoongArch] Support la664 (#100068)Ami-zhang1-0/+2
A new ProcessorModel called `la664` is defined in LoongArch.td to support `-march/-mtune=la664`.
2024-07-23[RISCV] Mark zacas as experimental again due to unresolved ABI issue (#99898)Alex Bradbury1-1/+2
As discussed at the last sync-up call, mark Zacas as experimental until this ABI issue is resolved <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/444>. Don't return Zacas in getHostCPUFeatures (leaving a TODO there) as even if requesting detection of "native" features, the user likely doesn't want to automatically opt in to experimental codegen.
2024-07-16[RISCV] Add support for getHostCPUFeatures using hwprobe (#94352)Yingwei Zheng1-4/+75
This patch adds support for `sys::getHostCPUFeatures` using the RISC-V hardware probing interface. References: + Loongarch patch: https://github.com/llvm/llvm-project/commit/e53f41c39f3eb5052965c720d2cb517d2945fd12 + asm/hwprobe.h: https://github.com/torvalds/linux/blob/2ab79514109578fc4b6df90633d500cf281eb689/arch/riscv/include/uapi/asm/hwprobe.h + glibc support: https://inbox.sourceware.org/glibc-cvs/20240301151728.AD5963858C53@sourceware.org/T/#Z2e.:..:20240301151728.AD5963858C53::40sourceware.org:1sysdeps:unix:sysv:linux:riscv:sys:hwprobe.h + __NR_riscv_hwprobe syscall tutorial: https://github.com/cyyself/hwprobe + hwprobe docs: https://docs.kernel.org/arch/riscv/hwprobe.html --------- Co-authored-by: Yangyu Chen <cyy@cyyself.name>
2024-07-11[llvm][TargetParser] Return StringMap from getHostCPUFeatures (#97824)David Spickett1-11/+17
Previously this took a reference to a map and returned a bool to say whether it succeeded. We can return a StringMap instead, as all callers but 1 simply iterated the map if the bool was true, and passed in empty maps as the starting point. lldb's lit-cpuid did specifically check whether the call failed, but due to the way the x86 routines work this works out the same as checking if the returned map is empty.
2024-07-09Revert "[compiler-rt][X86] Use functions in cpuid.h instead of inline ↵Aiden Grossman1-16/+78
assembly (#97877)" This reverts commit f6616e99c71c15d530060346ec29c3246d7fc235. Was causing buildbot failures on Windows. I also remember seeing a AMDGPU buildbot failing somewhere on a warning as they have -Werror enabled.
2024-07-08Reland "Revert "[compiler-rt][X86] Use functions in cpuid.h instead of ↵Aiden Grossman1-78/+16
inline assembly (#97877)"" This reverts commit 2039e130649d8469bc85fa31ba7422d1d3739f90. This relands commit 19cf8deabe1124831164987f1b9bf2f806c0a875. Added some additional preprocessor directives to ensure that Host.cpp only includes cpuid.h when being built on x86.
2024-07-08Remove an extra tokens at end of #undef directive, NFCHaojian Wu1-1/+1
2024-07-08[compiler-rt][X86] Unify getAMDProcessorTypeAndSubType (#97863)Aiden Grossman1-17/+15
This patch unifies the implementation of getAMDProcessorTypeAndSubtype between compiler-rt and LLVM. This patch is intended to be a step towards pulling these functions out into identical .inc files to better facilitate code sharing between LLVM and compiler-rt.
2024-07-08Revert "[compiler-rt][X86] Use functions in cpuid.h instead of inline ↵Aiden Grossman1-14/+78
assembly (#97877)" This reverts commit 19cf8deabe1124831164987f1b9bf2f806c0a875. This was causing quite a few buildbot failures (see the PR description). Reverting for now while I have time to sort it out. Seems like it should just be conditional preprocessor macros for X86 however.
2024-07-08[compiler-rt][X86] Use functions in cpuid.h instead of inline assembly (#97877)Aiden Grossman1-78/+14
This patch makes the host/feature detection in compiler-rt and LLVM use the functions provided in cpuid.h(__get_cpuid, __get_cpuid_count) instead of inline assembly. This simplifies the implementation and moves any inline assembly away to a more common place. A while ago, some similar cleanup was attempted, but this ended up resulting in some compilation errors due to toolchain minimum version issues (https://bugs.llvm.org/show_bug.cgi?id=30384). After the reversion landed, there have been no attempts since then to clean up the code, even though the minimum supported compilers now support the relevant functions (https://godbolt.org/z/o1Mjz8ndv).
2024-06-13[AArch64] Add support for Cortex-A725 and Cortex-X925 (#95214)Jonathan Thackray1-0/+2
Cortex-A725 and Cortex-X925 are Armv9.2 AArch64 CPUs. Technical Reference Manual for Cortex-A725: https://developer.arm.com/documentation/107652/latest Technical Reference Manual for Cortex-X925: https://developer.arm.com/documentation/102807/latest
2024-06-07[ARM] Add support for Cortex-R52+ (#94633)Jonathan Thackray1-0/+1
Cortex-R52+ is an Armv8-R AArch32 CPU. Technical Reference Manual for Cortex-R52+: https://developer.arm.com/documentation/102199/latest/
2024-06-06[AArch64] Add support for Qualcomm Oryon processor (#91022)Wei Zhao1-0/+1
Oryon is an ARM V8 AArch64 CPU from Qualcomm. --------- Co-authored-by: Wei Zhao <wezhao@qti.qualcomm.com>
2024-05-24Reland "[X86] Remove knl/knm specific ISAs supports (#92883)" (#93136)Freddy Ye1-9/+0
This reverts commit aa4069ea96e5eb62bc8c7895b9d920f129611b3a.
2024-05-23Revert "[X86] Remove knl/knm specific ISAs supports (#92883)" (#93123)Freddy Ye1-0/+9
This reverts commit 282d2ab58f56c89510f810a43d4569824a90c538.
2024-05-23[X86] Remove knl/knm specific ISAs supports (#92883)Freddy Ye1-9/+0
Cont. patch after https://github.com/llvm/llvm-project/pull/75580
2024-05-10[X86][Driver] Do not add `-evex512` for `-march=native` when the target ↵Phoebe Wang1-1/+2
doesn't support AVX512 (#91694)
2024-04-30[AArch64] Add support for Cortex-R82AE and improve Cortex-R82 (#90440)Jonathan Thackray1-0/+1
2024-04-30[X86] Enable EVEX512 when host CPU has AVX512 (#90479)Phoebe Wang1-1/+4
This is used when -march=native run on an unknown CPU to old version of LLVM.
2024-04-26[AArch64] Add support for Neoverse-N3, Neoverse-V3 and Neoverse-V3AE (#90143)Jonathan Thackray1-0/+3
Neoverse-N3, Neoverse-V3 and Neoverse-V3AE are Armv9.2 AArch64 CPUs. Technical Reference Manual for Neoverse-N3: https://developer.arm.com/documentation/107997/latest/ Technical Reference Manual for Neoverse-V3: https://developer.arm.com/documentation/107734/latest/ Technical Reference Manual for Neoverse-V3AE: https://developer.arm.com/documentation/101595/latest/
2024-03-19[AArch64] Add support for Cortex-A520AE and Cortex-A720AE CPUs (#85401)Jonathan Thackray1-0/+2
[AArch64] Add support for Cortex-A520AE and Cortex-A720AE CPUs Cortex-A520AE and Cortex-A720AE are Armv9.2 AArch64 CPUs. Technical Reference Manual for Cortex-A520AE: https://developer.arm.com/documentation/107726/latest/ Technical Reference Manual for Cortex-A720AE: https://developer.arm.com/documentation/102828/latest/
2024-03-13[ARM][AArch64] Add missing Arm CPU part-ids to enable -mcpu=native (#84899)Jonathan Thackray1-0/+15
Update Host.cpp with some missing Arm CPU part identifiers, to enable `-mcpu=native` on these processors. These are found in the Technical Reference Manuals listed under "part num" or "part no"
2024-03-08Update host CPU detection for Apple M2 and Apple M3 (#82100)Mads Marquart1-1/+7
`CPUFAMILY_ARM_BLIZZARD_AVALANCHE` and `CPUFAMILY_ARM_EVEREST_SAWTOOTH` are taken from `<mach/machine.h>` in `Kernel.framework`.
2024-03-08Add support for Arm Cortex A78AE CPU (#84485)Jonathan Thackray1-0/+1
Add support for Arm Cortex A78AE CPU Technical Reference Manual for Arm Cortex A78AE: https://developer.arm.com/documentation/101779/0003 Fixes #84450
2024-02-23[X86] Support APXF to enable __builtin_cpu_supports. (#80636)Freddy Ye1-0/+7
For referring, APX's spec: https://cdrdv2.intel.com/v1/dl/getContent/784266 APX's index in libgcc: https://github.com/gcc-mirror/gcc/blob/master/gcc/common/config/i386/i386-cpuinfo.h#L267
2024-02-09[AArch64] Add the Ampere1B core (#81297)Philipp Tomsich1-0/+1
The Ampere1B is Ampere's third-generation core implementing a superscalar, out-of-order microarchitecture with nested virtualization, speculative side-channel mitigation and architectural support for defense against ROP/JOP style software attacks. Ampere1B is an ARMv8.7+ implementation, adding support for the FEAT WFxT, FEAT CSSC, FEAT PAN3 and FEAT AFP extensions. It also includes all features of the second-generation Ampere1A, such as the Memory Tagging Extension and SM3/SM4 cryptography instructions.
2024-01-16[AArch64] Add native CPU detection for Microsoft Azure Cobalt 100. (#77793)Alexandros Lamprineas1-0/+7
This patch extends the -mcpu/mtune=native support to handle the Microsoft Azure Cobalt 100 CPU as a Neoverse N2. We expect users to use -mcpu=neoverse-n2 when targeting this CPU and all the architecture and codegen decisions to be identical. The only difference is that the Microsoft Azure Cobalt 100 has a different Implementer ID in the /proc/cpuinfo entry that needs to be detected in getHostCPUNameForARM appropriately.
2024-01-03[LoongArch] Fix the procossor series maskWeining Lu1-1/+2
Refer PRID_SERIES_MASK definition in linux kernel: arch/loongarch/include/asm/cpu.h.
2023-12-29[X86] Fix warning in cpu detection due to unsigned comparisonAiden Grossman1-1/+1
a15532d7647a8a4b7fd2889bd97f6f72f273c4bf landed a patch that added support for detecting more AMD znver2 CPUs and cleaned up some of the surrounding code, including the znver3 detection. Since one model group is 00h-0fh, I adjusted the check to include checking if the value is greater than zero. Since the value is unsigned, this is always true and gcc warns on it. This patch removes the comparison with zero to get rid of the compiler warning.
2023-12-21[X86] Add CPU detection for more znver2 CPUs (#74955)Aiden Grossman1-15/+37
This patch adds proper detection support for more znver2 CPUs. Specifically, this adds in support for CPUs codenamed Renoir, Lucienne, and Mendocino. This was originally proposedfor Renoir in https://reviews.llvm.org/D96220 and got approved, but slipped through the cracks. However, there is still a demand for this feature. In addition to adding support for more znver2 CPUs, this patch also includes some additional refactoring and comments related to cpu model information for zen CPUs. Fixes https://github.com/llvm/llvm-project/issues/74934.
2023-12-16[llvm] Use StringRef::{starts,ends}_with (NFC)Kazu Hirata1-2/+2
This patch replaces uses of StringRef::{starts,ends}with with StringRef::{starts,ends}_with for consistency with std::{string,string_view}::{starts,ends}_with in C++20. I'm planning to deprecate and eventually remove StringRef::{starts,ends}with.
2023-12-11[llvm] Use StringRef::{starts,ends}_with (NFC) (#74956)Kazu Hirata1-7/+7
This patch replaces uses of StringRef::{starts,ends}with with StringRef::{starts,ends}_with for consistency with std::{string,string_view}::{starts,ends}_with in C++20. I'm planning to deprecate and eventually remove StringRef::{starts,ends}with.
2023-12-08[ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (#74822)Jonathan Thackray1-0/+1
Cortex-M52 is an Armv8.1 AArch32 CPU. Technical specifications available at: https://developer.arm.com/processors/cortex-m52
2023-11-16[AArch64] Add support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs (#72395)Jonathan Thackray1-0/+3
Cortex-A520, Cortex-A720 and Cortex-X4 are Armv9.2 AArch64 CPUs. Technical Reference Manual for Cortex-A520: https://developer.arm.com/documentation/102517/latest/ Technical Reference Manual for Cortex-A720: https://developer.arm.com/documentation/102530/latest/ Technical Reference Manual for Cortex-X4: https://developer.arm.com/documentation/102484/latest/ Patch co-authored by: Sivan Shani <sivan.shani@arm.com>
2023-10-19[X86] Support -march=pantherlake,clearwaterforest (#69277)Freddy Ye1-0/+13
2023-10-19[X86][RFC] Support AVX10 options (#67278)Phoebe Wang1-0/+6
AVX10 Architecture Specification: https://cdrdv2.intel.com/v1/dl/getContent/784267 AVX10 Technical Paper: https://cdrdv2.intel.com/v1/dl/getContent/784343 RFC: https://discourse.llvm.org/t/rfc-design-for-avx10-options-support/73672
2023-10-16[X86] Add USER_MSR instructions. (#68944)Freddy Ye1-0/+1
For more details about this instruction, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
2023-09-27Add missed Darwin/i386 for `withHostArch` (#67617)Kirill A. Korinsky1-0/+3
This regression was introduced at LLVM-17 via dc078e6eaacff66596fac76b6104aa504f77d45d
2023-09-26[X86] Add detection for more Tremont models (#67150)libenc1-0/+3
Fix the issue that only the server series Tremont processors (Snow Ridge & Elkhart Lake) can be detected as Tremont, while the client series (Jasper Lake & Lakefield) will be guessed as Goldmont. Noted that Lakefield is missing some features compare to other Tremont processors, but those features are also missing on `FeatureTremont`, which shouldn't be a problem. Those features are `waitpkg`, `movdiri` and `movdir64b`.
2023-08-21[X86] Support -march=gracemontFreddy Ye1-0/+2
gracemont has some different tuning features from alderlake. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D158046
2023-08-03[X86] Workaround possible CPUID bug in Sandy Bridge.Craig Topper1-2/+8
Don't access leaf 7 subleaf 1 unless subleaf 0 says it is supported via EAX. Intel documentation says invalid subleaves return 0. We had been relying on that behavior instead of checking the max sublef number. It appears that some Sandy Bridge CPUs return at least the subleaf 0 EDX value for subleaf 1. Best guess is that this is a bug in a microcode patch since all of the bits we're seeing set in EDX were introduced after Sandy Bridge was originally released. This is causing avxvnniint16 to be incorrectly enabled with -march=native on these CPUs. Reviewed By: pengfei, anna Differential Revision: https://reviews.llvm.org/D156963
2023-07-28[X86] Support -march=arrowlake,arrowlake-s,lunarlakeFreddy Ye1-0/+16
Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D156239
2023-07-26[X86] Update Model value for Raptor Lake.Freddy Ye1-0/+2
Reviewed By: pengfei, skan Differential Revision: https://reviews.llvm.org/D156285
2023-07-25[X86] Support -march=graniterapids-d and update -march=graniterapidsFreddy Ye1-1/+7
Reviewed By: pengfei, RKSimon, skan Differential Revision: https://reviews.llvm.org/D155798
2023-07-20[X86] Add AVX-VNNI-INT16 instructions.Freddy Ye1-0/+1
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html Reviewed By: pengfei, skan Differential Revision: https://reviews.llvm.org/D155145
generated by cgit v1.1 at 2025-09-29 09:09:10 +0000