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2012-11-30Codegen failure for vmull with small vectorsSebastian Pop1-13/+74
Codegen was failing with an assertion because of unexpected vector operands when legalizing the selection DAG for a MUL instruction. The asserting code was legalizing multiplies for vectors of size 128 bits. It uses a custom lowering to try and detect cases where it can use a VMULL instruction instead of a VMOVL + VMUL. The code was looking for input operands to the MUL that had been sign or zero extended. If it found the extended operands it would drop the sign/zero extension and use the original vector size as input to a VMULL instruction. The code assumed that the original input vector was 64 bits so that after dropping the extension it would fit directly into a D register and could be used as an operand of a VMULL instruction. The input code that trigger the failure used a vector of <4 x i8> that was sign extended to <4 x i32>. It was not safe to drop the sign extension in this case because the original vector is only 32 bits wide. The fix is to insert a sign extension for the vector to reach the required 64 bit size. In this particular example, the vector would need to be sign extented to a <4 x i16>. llvm-svn: 169024
2012-11-30Use multiclass for the load instructions with MEMri operand.Jyotsna Verma1-184/+66
llvm-svn: 169018
2012-11-30This patch fixes the Altivec addend construction for the fused multiply-addAdhemerval Zanella1-5/+7
instruction (vmaddfp) to conform with IEEE to ensure the sign of a zero result when resulting product is -0.0. The -0.0 vector addend to vmaddfp is generated by a creating a vector with full bits sets and then shifting each elements by 31-bits to the left, resulting in a vector of 0x80000000 (or -0.0 as float). The 'buildvec_canonicalize.ll' was adjusted to reflect this change and the 'vec_mul.ll' was complemented with the float vector multiplication test. llvm-svn: 168998
2012-11-30Switch LLVM_USE_RVALUE_REFERENCES to LLVM_HAS_RVALUE_REFERENCES.Chandler Carruth1-1/+1
Rationale: 1) This was the name in the comment block. ;] 2) It matches Clang's __has_feature naming convention. 3) It matches other compiler-feature-test conventions. Sorry for the noise. =] I've also switch the comment block to use a \brief tag and not duplicate the name. llvm-svn: 168996
2012-11-30Use multiclass for the store instructions with MEMri operand.Jyotsna Verma2-163/+64
llvm-svn: 168983
2012-11-30Use multiclass for the load instructions with 'base + register offset'Jyotsna Verma1-277/+97
addressing mode. llvm-svn: 168976
2012-11-29Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInstKevin Enderby1-1/+7
which would then cause an assert when printed. rdar://11437956 llvm-svn: 168960
2012-11-29Add cortex-a5 subtarget to the supported ARM architecturesQuentin Colombet2-1/+12
llvm-svn: 168933
2012-11-29rdar://12100355 (part 1)Shuxin Yang3-1/+20
This revision attempts to recognize following population-count pattern: while(a) { c++; ... ; a &= a - 1; ... }, where <c> and <a>could be used multiple times in the loop body. TODO: On X8664 and ARM, __buildin_ctpop() are not expanded to a efficent instruction sequence, which need to be improved in the following commits. Reviewed by Nadav, really appreciate! llvm-svn: 168931
2012-11-29Use multiclass for 'transfer' instructions.Jyotsna Verma2-80/+98
llvm-svn: 168929
2012-11-29Added atomic 64 min/max/umin/umax instrinsics support in the ARM backend.Silviu Baranga4-12/+102
llvm-svn: 168886
2012-11-29Allow targets to prefer TypeSplitVector over TypePromoteInteger when ↵Justin Holewinski2-0/+7
computing the legalization method for vectors For some targets, it is desirable to prefer scalarizing <N x i1> instead of promoting to a larger legal type, such as <N x i32>. llvm-svn: 168882
2012-11-29I changed hasAVX() to hasFp256() and hasAVX2() to hasInt256() in ↵Elena Demikhovsky2-102/+104
X86IselLowering.cpp. The logic was not changed, only names. llvm-svn: 168875
2012-11-28Define signed const-ext immediate operands and their predicates.Jyotsna Verma2-0/+122
llvm-svn: 168810
2012-11-28ARM: Implement CanLowerReturn so large vectors get expanded into sret.Benjamin Kramer2-0/+17
Fixes 14337. llvm-svn: 168809
2012-11-28Fix initial frame state on powerpc64.Ulrich Weigand1-1/+1
The createPPCMCAsmInfo routine used PPC::R1 as the initial frame pointer register, but on PPC64 the 32-bit R1 register does not have a corresponding DWARF number, causing invalid CIE initial frame state to be emitted. Fix by using PPC::X1 instead. llvm-svn: 168799
2012-11-28Remove all references to TargetInstrInfoImpl.Jakob Stoklund Olesen4-12/+12
This class has been merged into its super-class TargetInstrInfo. llvm-svn: 168760
2012-11-28Move Target{Instr,Register}Info.cpp into lib/CodeGen.Jakob Stoklund Olesen3-338/+0
The Target library is not allowed to depend on the large CodeGen library, but the TRI and TII classes provide abstract interfaces that require both caller and callee to link to CodeGen. The implementation files for these classes provide default implementations of some of the hooks. These methods may need to reference CodeGen, so they belong in that library. We already have a number of methods implemented in the TargetInstrInfoImpl sub-class because of that. I will merge that class into the parent next. llvm-svn: 168758
2012-11-27This patch makes medium code model the default for 64-bit PowerPC ELF.Bill Schmidt1-0/+5
When the CodeGenInfo is to be created for the PPC64 target machine, a default code-model selection is converted to CodeModel::Medium provided we are not targeting the Darwin OS. Defaults for Darwin are unaffected. llvm-svn: 168747
2012-11-27[arm fast-isel] Appease the machine verifier by using the proper registerChad Rosier1-9/+7
classes. The vast majority of the remaining issues are due to uses of invalid registers, which are defined by getRegForValue(). Those will be a little more challenging to cleanup. rdar://12719844 llvm-svn: 168735
2012-11-27[arm fast-isel] Appease the machine verifier by using the proper registerChad Rosier1-2/+4
classes. rdar://12719844 llvm-svn: 168733
2012-11-27[arm fast-isel] Appease the machine verifier by using the proper registerChad Rosier1-5/+6
classes. Also a bit of cleanup. rdar://12719844 llvm-svn: 168728
2012-11-27X86: do not fold load instructions such as [V]MOVS[S|D] to other instructionsManman Ren1-0/+15
when the destination register is wider than the memory load. These load instructions load from m32 or m64 and set the upper bits to zero, while the folded instructions may accept m128. rdar://12721174 llvm-svn: 168710
2012-11-27This patch implements medium code model support for 64-bit PowerPC.Bill Schmidt7-10/+233
The default for 64-bit PowerPC is small code model, in which TOC entries must be addressable using a 16-bit offset from the TOC pointer. Additionally, only TOC entries are addressed via the TOC pointer. With medium code model, TOC entries and data sections can all be addressed via the TOC pointer using a 32-bit offset. Cooperation with the linker allows 16-bit offsets to be used when these are sufficient, reducing the number of extra instructions that need to be executed. Medium code model also does not generate explicit TOC entries in ".section toc" for variables that are wholly internal to the compilation unit. Consider a load of an external 4-byte integer. With small code model, the compiler generates: ld 3, .LC1@toc(2) lwz 4, 0(3) .section .toc,"aw",@progbits .LC1: .tc ei[TC],ei With medium model, it instead generates: addis 3, 2, .LC1@toc@ha ld 3, .LC1@toc@l(3) lwz 4, 0(3) .section .toc,"aw",@progbits .LC1: .tc ei[TC],ei Here .LC1@toc@ha is a relocation requesting the upper 16 bits of the 32-bit offset of ei's TOC entry from the TOC base pointer. Similarly, .LC1@toc@l is a relocation requesting the lower 16 bits. Note that if the linker determines that ei's TOC entry is within a 16-bit offset of the TOC base pointer, it will replace the "addis" with a "nop", and replace the "ld" with the identical "ld" instruction from the small code model example. Consider next a load of a function-scope static integer. For small code model, the compiler generates: ld 3, .LC1@toc(2) lwz 4, 0(3) .section .toc,"aw",@progbits .LC1: .tc test_fn_static.si[TC],test_fn_static.si .type test_fn_static.si,@object .local test_fn_static.si .comm test_fn_static.si,4,4 For medium code model, the compiler generates: addis 3, 2, test_fn_static.si@toc@ha addi 3, 3, test_fn_static.si@toc@l lwz 4, 0(3) .type test_fn_static.si,@object .local test_fn_static.si .comm test_fn_static.si,4,4 Again, the linker may replace the "addis" with a "nop", calculating only a 16-bit offset when this is sufficient. Note that it would be more efficient for the compiler to generate: addis 3, 2, test_fn_static.si@toc@ha lwz 4, test_fn_static.si@toc@l(3) The current patch does not perform this optimization yet. This will be addressed as a peephole optimization in a later patch. For the moment, the default code model for 64-bit PowerPC will remain the small code model. We plan to eventually change the default to medium code model, which matches current upstream GCC behavior. Note that the different code models are ABI-compatible, so code compiled with different models will be linked and execute correctly. I've tested the regression suite and the application/benchmark test suite in two ways: Once with the patch as submitted here, and once with additional logic to force medium code model as the default. The tests all compile cleanly, with one exception. The mandel-2 application test fails due to an unrelated ABI compatibility with passing complex numbers. It just so happens that small code model was incredibly lucky, in that temporary values in floating-point registers held the expected values needed by the external library routine that was called incorrectly. My current thought is to correct the ABI problems with _Complex before making medium code model the default, to avoid introducing this "regression." Here are a few comments on how the patch works, since the selection code can be difficult to follow: The existing logic for small code model defines three pseudo-instructions: LDtoc for most uses, LDtocJTI for jump table addresses, and LDtocCPT for constant pool addresses. These are expanded by SelectCodeCommon(). The pseudo-instruction approach doesn't work for medium code model, because we need to generate two instructions when we match the same pattern. Instead, new logic in PPCDAGToDAGISel::Select() intercepts the TOC_ENTRY node for medium code model, and generates an ADDIStocHA followed by either a LDtocL or an ADDItocL. These new node types correspond naturally to the sequences described above. The addis/ld sequence is generated for the following cases: * Jump table addresses * Function addresses * External global variables * Tentative definitions of global variables (common linkage) The addis/addi sequence is generated for the following cases: * Constant pool entries * File-scope static global variables * Function-scope static variables Expanding to the two-instruction sequences at select time exposes the instructions to subsequent optimization, particularly scheduling. The rest of the processing occurs at assembly time, in PPCAsmPrinter::EmitInstruction. Each of the instructions is converted to a "real" PowerPC instruction. When a TOC entry needs to be created, this is done here in the same manner as for the existing LDtoc, LDtocJTI, and LDtocCPT pseudo-instructions (I factored out a new routine to handle this). I had originally thought that if a TOC entry was needed for LDtocL or ADDItocL, it would already have been generated for the previous ADDIStocHA. However, at higher optimization levels, the ADDIStocHA may appear in a different block, which may be assembled textually following the block containing the LDtocL or ADDItocL. So it is necessary to include the possibility of creating a new TOC entry for those two instructions. Note that for LDtocL, we generate a new form of LD called LDrs. This allows specifying the @toc@l relocation for the offset field of the LD instruction (i.e., the offset is replaced by a SymbolLo relocation). When the peephole optimization described above is added, we will need to do similar things for all immediate-form load and store operations. The seven "mcm-n.ll" test cases are kept separate because otherwise the intermingling of various TOC entries and so forth makes the tests fragile and hard to understand. The above assumes use of an external assembler. For use of the integrated assembler, new relocations are added and used by PPCELFObjectWriter. Testing is done with "mcm-obj.ll", which tests for proper generation of the various relocations for the same sequences tested with the external assembler. llvm-svn: 168708
2012-11-27Remove the dependent libraries feature.Bill Wendling1-8/+0
The dependent libraries feature was never used and has bit-rotted. Remove it. llvm-svn: 168694
2012-11-27[arm fast-isel] Appease the machine verifier by using the proper registerChad Rosier1-4/+10
classes. The associated test case still doesn't pass, but it does have far fewer issues. rdar://12719844 llvm-svn: 168657
2012-11-26Remove the X86 Maximal Stack Alignment Check pass as it is no longer necessary.Chad Rosier3-50/+0
This pass was conservative in that it always reserved the FP to enable dynamic stack realignment, which allowed the RA to use aligned spills for vector registers. This happens even when spills were not necessary. The RA has since been improved to use unaligned spills when necessary. The new behavior is to realign the stack if the frame pointer was already reserved for some other reason, but don't reserve the frame pointer just because a function contains vector virtual registers. Part of rdar://12719844 llvm-svn: 168627
2012-11-26Fix comments in HexagonOperands.td.Jyotsna Verma1-29/+27
llvm-svn: 168617
2012-11-26Normalize splat 256bit vectors with 8 elements.Jakub Staszak1-1/+1
llvm-svn: 168600
2012-11-26Decouple MCInstBuilder from the streamer per Eli's request.Benjamin Kramer3-156/+111
llvm-svn: 168597
2012-11-26Add MCInstBuilder, a utility class to simplify MCInst creation similar to ↵Benjamin Kramer3-486/+373
MachineInstrBuilder. Simplify some repetitive code with it. No functionality change. llvm-svn: 168587
2012-11-24PPC: Reinstate the fatal error when trying to emit a macho file.Benjamin Kramer1-1/+3
llvm-svn: 168543
2012-11-24ARM: Share applyFixup between ELF and Darwin.Benjamin Kramer1-63/+46
The implementations already diverged a bit, merge them back together. llvm-svn: 168542
2012-11-24PPC: MCize most of the darwin PIC emission.Benjamin Kramer1-35/+92
The last remaining bit is "bcl 20, 31, AnonSymbol", which I couldn't find the instruction definition for. Only whitespace changes in assembly output. llvm-svn: 168541
2012-11-24PPC: Share applyFixup between ELF and Darwin.Benjamin Kramer1-18/+14
llvm-svn: 168540
2012-11-24PPC: Simplify code with Twines.Benjamin Kramer1-6/+3
No functionality change. llvm-svn: 168539
2012-11-23Update call to the new syntax.Bill Wendling1-1/+1
llvm-svn: 168512
2012-11-22Add more functions to the target library information.Meador Inge1-0/+47
I discovered a few more missing functions while migrating optimizations from the simplify-libcalls pass to the instcombine (I already added some in r167659). llvm-svn: 168501
2012-11-21Mips direct object xgot supportJack Carter4-1/+45
This patch provides support for the MIPS relocations: *) R_MIPS_GOT_HI16 *) R_MIPS_GOT_LO16 *) R_MIPS_CALL_HI16 *) R_MIPS_CALL_LO16 These are used for large GOT instruction sequences. Contributer: Jack Carter llvm-svn: 168471
2012-11-21[mips] Generate big GOT code.Akira Hatanaka5-3/+25
llvm-svn: 168460
2012-11-21[mips] Simplify lowering functions in MipsISelLowering.cpp by using the helperAkira Hatanaka1-148/+32
functions added in r168456. llvm-svn: 168458
2012-11-21[mips] Add helper functions that create nodes for computing address.Akira Hatanaka1-0/+65
llvm-svn: 168456
2012-11-21[mips] Add command line option "-mxgot".Akira Hatanaka1-0/+4
llvm-svn: 168455
2012-11-21[mips] When a node which loads from a GOT is created, pass a MachinePointerInfoAkira Hatanaka1-4/+6
referring to a GOT entry. llvm-svn: 168453
2012-11-21Add new predicates for the immediate operands.Jyotsna Verma1-4/+121
llvm-svn: 168451
2012-11-21[mips] Add target operand flag enums for big GOT relocations.Akira Hatanaka1-1/+7
llvm-svn: 168450
2012-11-21Use one common 'let' expression to set PrintMethod for all immediate operands.Jyotsna Verma1-209/+53
llvm-svn: 168449
2012-11-21Add support for varargs functions for msp430.Anton Korobeynikov3-2/+36
Patch by Job Noorman! llvm-svn: 168440
2012-11-21Add support for byval args. Patch by Job Noorman!Anton Korobeynikov2-17/+46
llvm-svn: 168439
2012-11-21Finish the renaming.Rafael Espindola2-2/+2
llvm-svn: 168437
generated by cgit v1.1 at 2025-10-17 14:37:23 +0000