riscv-gnu-toolchain/llvm.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2026-01-13	fixed a comment.users/cdevadas/make-getNumSubRegsForSpillOp-member-function	Christudasan Devadasan	1	-1/+1
2026-01-13	moved the implementation to SIInstrInfo.	Christudasan Devadasan	4	-151/+150
2026-01-13	[AMDGPU] Make getNumSubRegsForSpillOp externally available (NFC).	Christudasan Devadasan	2	-3/+5
2026-01-13	incorporated review comments.users/cdevadas/add-spill-offset-to-sgpr-spill-pseudos	Christudasan Devadasan	1	-3/+3
2026-01-13	[AMDGPU] Introduce Offset field in SGPR spill Pseudos	Christudasan Devadasan	3	-6/+8
2026-01-13	[CodeGen][InlineSpiller] Add SubReg argument to loadRegFromStackSlot for subr...	Christudasan Devadasan	47	-50/+57
2026-01-12	[RISCV] Add the missing SEW search table field to vector FMA instructions (#1...	Min-Yih Hsu	1	-1/+1
2026-01-13	[AMDGPU]Add specific instruction feature for multicast load (#175503)	Shoreshen	3	-3/+16
2026-01-13	[RISCV] Adjust base cost for Xqcilo loads/stores in RISCVMakeCompressible (#1...	Sudharsan Veeravalli	1	-7/+38
2026-01-13	[RISCV] Use LD_RV32/SD_RV32 for spills and reloads when Zilsd is enabled (#15...	Sudharsan Veeravalli	1	-6/+18
2026-01-12	[llvm][RISCV] Suppress unused `IsMulH` warning. (#175653)	Chenguang Wang	1	-2/+3
2026-01-12	[X86][NewPM] Port x86-pre-tile-config (#175649)	Aiden Grossman	4	-23/+57
2026-01-12	[X86][NewPM] Port x86-tile-config (#175647)	Aiden Grossman	4	-18/+45
2026-01-12	[AMDGPU] Add DS loop waitcnt optimization for GFX12+ (#172728)	hidekisaito	1	-61/+164
2026-01-12	[X86][NewPM] Port x86-fixup-vector-constants (#175622)	Aiden Grossman	4	-20/+49
2026-01-12	[X86][NewPM] Port x86-suppress-apx-for-relocation (#175634)	Aiden Grossman	4	-14/+36
2026-01-12	[X86][NewPM] Port x86-lower-tile-copy (#175625)	Aiden Grossman	4	-14/+32
2026-01-12	[X86][NewPM] Port x86-fixup-setcc (#175609)	Aiden Grossman	4	-21/+33
2026-01-12	[AMDGPU]: Rewrite mbcnt_lo/mbcnt_hi to work item ID where applicable (#160496)	Teja Alaghari	1	-0/+116
2026-01-12	[DirectX] Update DXILValueEnumerator for the new SwitchInst format (#174672)	Deric C.	1	-0/+8
2026-01-12	[NVPTX] Validate user-specified PTX version against SM version (#174834)	Justin Fargnoli	3	-61/+108
2026-01-12	[RISCV] Add isel patterns for ANDN/ORN/XNOR with P+Zbb. (#175384)	Craig Topper	1	-0/+15
2026-01-12	[llvm][RISCV] Support rounding mulh for P extension codegen (#171593)	Brandon Wu	2	-13/+63
2026-01-12	[NFC][LLVM][AArch64] Simplify `checkPartialMappingIdx` (#173050)	Rahul Joshi	1	-6/+1
2026-01-12	[RISCV] Detect QC_E_ADDAI and fold in RISCVMergeBaseOffset (#175496)	Sudharsan Veeravalli	1	-1/+2
2026-01-12	[AArch64] Define cost of i16->i32 udot/sdot instructions (#174102)	Sander de Smalen	1	-0/+5
2026-01-12	[X86][NewPM] Port x86-fixup-inst-tuning (#175576)	Aiden Grossman	4	-18/+50
2026-01-12	[SPIRV] Deduce result type for `G_SEXT` and `G_ZEXT` (#175401)	Alex Voicu	1	-0/+2
2026-01-12	[AArch64] Add support for range prefetch intrinsic (#170490)	Kerry McLaughlin	4	-0/+42
2026-01-12	[X86] InstCombine: Generalize scalar SSE MAX/MIN intrinsics (#175375)	Guilherme oliveira de campos	1	-9/+40
2026-01-12	[RISCV] Fix ReplaceNodeResults of Intrinsic::experimental_cttz_elts for RV32 ...	Alex Bradbury	1	-2/+1
2026-01-12	[AMDGPU] Fix crash in SIInsertWaitcnts debug output (#175518)	Jay Foad	1	-32/+28
2026-01-12	[AMDGPU] Inline two helpers in SIInsertWaitcnts. NFC. (#174557)	Jay Foad	1	-22/+9
2026-01-12	[PowerPC] using milicode call for strcpy instead of lib call (#174782)	zhijian lin	4	-5/+25
2026-01-12	[X86] Allow EVEX compression for VPMOV*2M + KMOV pattern (#175219)	Qihan Cai	1	-4/+151
2026-01-12	[InstCombine][X86] Move simplifyX86FPMaxMin handling from simplifyDemandedVec...	Simon Pilgrim	1	-26/+27
2026-01-12	[AMDGPU][SIInsertWaitcnt] Implement Waitcnt Expansion for Profiling (#169345)	Pankaj Dwivedi	3	-92/+242
2026-01-12	[AArch64][llvm] Add extra dependencies for recently added features (#175215)	Jonathan Thackray	1	-2/+2
2026-01-12	[LoongArch] Disable strict node mutation to fix strict FP lowering crash (#17...	hev	1	-0/+3
2026-01-12	[WebAssembly] vi8 mul cost modelling. (#175177)	Sam Parker	2	-3/+25
2026-01-12	[SPIR-V] Fix Linkage capability with pushconstant (#175192)	Nathan Gauër	1	-0/+1
2026-01-12	[Clang] Add `__builtin_stack_address` (#148281)	moorabbit	1	-0/+25
2026-01-12	[Aarch64] Add support for Ampere1C core (#175442)	Philipp Tomsich	2	-0/+26
2026-01-12	[AArch64] Update NZCV flag-setting instructions' throughput for Neoverse N2 (...	Amina Chabane	1	-4/+27
2026-01-12	[PowerPC] Optimize not equal compares against zero vectors (#150422)	Himadhith	1	-0/+14
2026-01-12	[RISCV][llvm] Support logical comparison codegen for P extension (#174626)	Brandon Wu	2	-0/+37
2026-01-12	[RISCV] Schedule RVV instructions with compatible vtype/vl first	Pengcheng Wang	3	-5/+120
2026-01-12	[RISCV][NFC] Add RISCVVSETVLIInfoAnalysis	Pengcheng Wang	6	-1030/+1116
2026-01-12	[RISCV] Add a custom pre-ra scheduler	Pengcheng Wang	4	-1/+158
2026-01-12	[RISCV] Add support for QC.E.LI in RISCVMergeBaseOffset (#175310)	Sudharsan Veeravalli	1	-38/+53