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2026-01-05[AMDGPU] Add new llvm.amdgcn.wave.shuffle intrinsic (#167372)saxlungs5-1/+223
2026-01-05[NFC][Hexagon] Fix unused variable warning (#174466)Aiden Grossman1-2/+3
2026-01-05Honor alignment for HVX masked loads/stores (incl. loops) (#174419)Fateme Hosseini1-41/+311
2026-01-05[AArch64] Make ISD::CTLS Legal for i32 and i64. (#174367)Craig Topper2-3/+9
2026-01-05[NFC][AMDGPU] Declare variables initialized with getDebugLoc as const ref (#1...LU-JOHN10-21/+21
2026-01-05[X86][NewPM] Port x86-fast-tile-config to NewPM (#174446)Aiden Grossman4-15/+40
2026-01-05[X86] combineConcatVectorOps - add missing X86ISD::CMPM handling (#174420)Simon Pilgrim1-0/+3
2026-01-05[AMDGPU] Generate more efficient code to avoid shift64 hazard (#171871)LU-JOHN1-11/+25
2026-01-05[AMDGPU] Make WaitcntBrackets::simplifyWaitcnt const again (#173390)Jay Foad1-47/+61
2026-01-05[AMDGPU] Simplify and document waitcnt handling on call and return (#172453)Jay Foad1-25/+5
2026-01-05[X86] combineConcatVectorOps - concat fma chains which share concatenated ope...Simon Pilgrim1-1/+19
2026-01-05[X86] combineConcatVectorOps - check for an existing operands concatenation (...Simon Pilgrim1-2/+6
2026-01-05[X86] combineSelect - replace manual constant pow2 checks and ctlz constant f...Simon Pilgrim1-14/+11
2026-01-05Revert "[AMDGPU] Fix excessive stack usage in SIInsertWaitcnts::run (#134835)...Jay Foad1-8/+3
2026-01-05[LLVM] Temporarily allow implicit truncation in some placesNikita Popov1-1/+4
2026-01-05[llvm][RISCV] Support fma codegen for zvfbfa (#172949)Brandon Wu3-35/+95
2026-01-04[RISCV][SelectionDAG] Add a ISD::CTLS node for count leading redundant sign b...Craig Topper2-4/+26
2026-01-05[RISCV] Update Andes45 vector load/stores scheduling info (#173806)Jim Lin1-25/+183
2026-01-04[X86][NewPM] Port x86-fast-pre-tile-config (#174323)Aiden Grossman4-27/+60
2026-01-04[X86] LowerMINMAX - use valuetracking to attempt to find a smaller type that ...Simon Pilgrim1-0/+32
2026-01-04[NFC] Delete unnecessary apostrophe at the end of its (#173974)willmafh2-2/+2
2026-01-04[X86] LowerShift - if a vXi8 shift amount is small enough skip additional inc...Simon Pilgrim1-37/+46
2026-01-04[X86][NewPM] Port x86-domain-reassignment (#174321)Aiden Grossman4-41/+71
2026-01-04[X86][NewPM] Port x86-cmov-conversion to NewPM (#174311)Aiden Grossman4-28/+56
2026-01-04[X86][NewPM] Port x86-compress-evex (#174312)Aiden Grossman4-12/+37
2026-01-04Revert "[AMDGPU] add clamp immediate operand to WMMA iu8 intrinsic (#171069)"...Shilei Tian1-3/+1
2026-01-03[RISCV] Support i32 SSHLAT for rv32ip. (#173687)Craig Topper2-1/+9
2026-01-03[X86][NewPM] Port x86-avoid-sfb to the New Pass Manager (#174166)Aiden Grossman4-36/+70
2026-01-03[X86] Avoid assertion failure with implicit immediates for AMX tile dimension...Thurston Dang1-1/+8
2026-01-03[X86] Cleanup uses of "(BW-1) - LOG2(C)" --> "CLZ(C)" instead. NFC. (#174167)Simon Pilgrim1-4/+3
2026-01-03[X86] combinePTESTCC - always prefer TESTPS/D to PTEST on AVX (#174097)Simon Pilgrim1-8/+10
2026-01-03[X86][AMX] Move Stride close to its use (#174095)Phoebe Wang1-4/+3
2026-01-02[LLVM][ADT] Migrate users of `make_scope_exit` to CTAD (#174030)Victor Chernyakin5-5/+5
2026-01-02[AArch64] Turn MaxInterleaveFactor into a subtarget feature (#171088)David Green3-39/+52
2026-01-02[NFC][AMDGPU] Add comments for literal arguments of WMMA profiles (#174175)Shilei Tian1-56/+77
2026-01-02[AArch64] Combine (not (shift X, C)) into MVN (#174180)Piotr Fusik1-0/+4
2026-01-01[X86][NewPM] Port x86-cf-opt to the New Pass Manager (#174168)Aiden Grossman4-31/+59
2026-01-02[RISCV][GISel] Support select vsetvli intrinsics (#174076)Jianjian Guan3-0/+89
2026-01-01[X86] combineSelect - pull out repeated getOperand() calls. NFC. (#174164)Simon Pilgrim1-4/+3
2026-01-01[AMDGPU][NPM] Disable few non useful passes (#172796)Vikram Hegde1-2/+2
2026-01-01[NVPTX] Add intrinsics and codegen for tensormap.replace (#172458)Srinivasa Ravi3-0/+177
2025-12-31[X86][NewPM] Port X86FixupLEAs to NPMAiden Grossman4-56/+98
2025-12-31[X86][NewPM] Port X86FlagsCopyLowering to NPMAiden Grossman4-33/+62
2025-12-31[X86][AMX-AVX512] Add *i intrinsics for immediate variants (#173545)Phoebe Wang5-9/+53
2025-12-31[Hexagon] TableGen-erate SDNode descriptions (#168272)Sergei Barannikov6-162/+143
2025-12-31[RISCV] Convert ORI with SingleBitSetMaskImm12 to BSETI when Xqcibm is enable...Sudharsan Veeravalli1-0/+9
2025-12-31[AArch64] - Allow for aggressive unrolling, with non-zero LoopMicroOpBufferS...Pawan Nirpal1-1/+1
2025-12-31[AMDGPU][NPM] add "addPostBBSections()" to NPM (#172793)Vikram Hegde1-0/+8
2025-12-30[RISCV] Use RVPTernary_rrr for accumulator instructions in RISCVInstrInfoP.td...Craig Topper1-3/+3
2025-12-30[HLSL] Add allresourcesbound option to DXC driver and set corresponding modul...Joshua Batista1-0/+7
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