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2016-09-13Defer asm errors to post-statement failureNirav Dave1-9/+7
Recommitting after fixing AsmParser Initialization. Allow errors to be deferred and emitted as part of clean up to simplify and shorten Assembly parser code. This will allow error messages to be emitted in helper functions and be modified by the caller which has better context. As part of this many minor cleanups to the Parser: * Unify parser cleanup on error * Add Workaround for incorrect return values in ParseDirective instances * Tighten checks on error-signifying return values for parser functions and fix in-tree TargetParsers to be more consistent with the changes. * Fix AArch64 test cases checking for spurious error messages that are now fixed. These changes should be backwards compatible with current Target Parsers so long as the error status are correctly returned in appropriate functions. Reviewers: rnk, majnemer Subscribers: aemerson, jyknight, llvm-commits Differential Revision: https://reviews.llvm.org/D24047 llvm-svn: 281336
2016-09-13Temporarily Revert "[MC] Defer asm errors to post-statement failure" as it's ↵Eric Christopher1-7/+9
causing errors on the sanitizer bots. This reverts commit r281249. llvm-svn: 281280
2016-09-12[MC] Defer asm errors to post-statement failureNirav Dave1-9/+7
Allow errors to be deferred and emitted as part of clean up to simplify and shorten Assembly parser code. This will allow error messages to be emitted in helper functions and be modified by the caller which has better context. As part of this many minor cleanups to the Parser: * Unify parser cleanup on error * Add Workaround for incorrect return values in ParseDirective instances * Tighten checks on error-signifying return values for parser functions and fix in-tree TargetParsers to be more consistent with the changes. * Fix AArch64 test cases checking for spurious error messages that are now fixed. These changes should be backwards compatible with current Target Parsers so long as the error status are correctly returned in appropriate functions. Reviewers: rnk, majnemer Subscribers: aemerson, jyknight, llvm-commits Differential Revision: https://reviews.llvm.org/D24047 llvm-svn: 281249
2016-09-09[Sparc][LEON] Removed the parts of the errata fixes implemented using inline ↵Chris Dewhurst1-76/+0
assembly as this is not the desired behaviour for end-users. Small change to a unit test to implement this without requiring the inline assembly. llvm-svn: 281047
2016-09-06[Sparc][Leon] Corrected supported atomics size for processors supporting ↵Chris Dewhurst1-1/+1
Leon CASA instruction back to 32 bits. This was erroneously checked-in for 64 bits while trying to find if there was a way to get 64 bit atomicity in Leon processors. There is not and this change should not have been checked-in. There is no unit test for this as the existing unit tests test for behaviour to 32 bits, which was the original intention of the code. llvm-svn: 280710
2016-09-02[Sparc] Mark i128 shift libcalls unavailable in 32-bit mode.James Y Knight1-0/+7
Recently, llvm wants to emit calls to these functions, while it didn't seem to be an issue before. Not sure why. Nor do I know why only these three are important to disable, out of all of the i128 libcalls. Nevertheless, many other targets have this snippet of code, so, just copying it to sparc as well, to unbreak things. llvm-svn: 280537
2016-08-29[Myriad]: add missing 'mcpu' valuesDouglas Katzman1-0/+3
Should have been done with r276646. llvm-svn: 279996
2016-08-25MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, ↵Matthias Braun1-1/+1
compute it Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of running after register and simply describes that no vregs are used in a machine function. With that we can simply compute the property and do not need to dump/parse it in .mir files. Differential Revision: http://reviews.llvm.org/D23850 llvm-svn: 279698
2016-08-18[SelectionDAG] Rename fextend -> fpextend, fround -> fpround, frnd -> froundMichael Kuperstein2-11/+11
The names of the tablegen defs now match the names of the ISD nodes. This makes the world a slightly saner place, as previously "fround" matched ISD::FP_ROUND and not ISD::FROUND. Differential Revision: https://reviews.llvm.org/D23597 llvm-svn: 279129
2016-08-17Replace a few more "fall through" comments with LLVM_FALLTHROUGHJustin Bogner1-13/+13
Follow up to r278902. I had missed "fall through", with a space. llvm-svn: 278970
2016-08-12Revert "[Sparc] Leon errata fix passes."James Y Knight8-947/+228
...and the two followup commits: Revert "[Sparc][Leon] Missed resetting option flags from check-in 278489." Revert "[Sparc][Leon] Errata fixes for various errata in different versions of the Leon variants of the Sparc 32 bit processor." This reverts commit r274856, r278489, and r278492. llvm-svn: 278511
2016-08-12[Sparc][Leon] Missed resetting option flags from check-in 278489.Chris Dewhurst1-0/+3
llvm-svn: 278492
2016-08-12[Sparc][Leon] Errata fixes for various errata in different versions of the ↵Chris Dewhurst7-230/+250
Leon variants of the Sparc 32 bit processor. The nature of the errata are listed in the comments preceding the errata fix passes. Relevant unit tests are implemented for each of these. These changes update older versions of these errata fixes with improvements to code and unit tests. Differential Revision: https://reviews.llvm.org/D21960 llvm-svn: 278489
2016-08-11Use the range variant of find instead of unpacking begin/endDavid Majnemer1-2/+1
If the result of the find is only used to compare against end(), just use is_contained instead. No functionality change is intended. llvm-svn: 278433
2016-07-28MachineFunction: Return reference for getFrameInfo(); NFCMatthias Braun3-56/+56
getFrameInfo() never returns nullptr so we should use a reference instead of a pointer. llvm-svn: 277017
2016-07-25MC] Provide an MCTargetOptions to implementors of MCAsmBackendCtorTy, NFCJoel Jones2-2/+5
Some targets, notably AArch64 for ILP32, have different relocation encodings based upon the ABI. This is an enabling change, so a future patch can use the ABIName from MCTargetOptions to chose which relocations to use. Tested using check-llvm. The corresponding change to clang is in: http://reviews.llvm.org/D16538 Patch by: Joel Jones Differential Revision: https://reviews.llvm.org/D16213 llvm-svn: 276654
2016-07-21[Sparc]: Fix bug in LowerSTORE due to r275592Douglas Katzman1-1/+1
llvm-svn: 276362
2016-07-15[SelectionDAG] Get rid of bool parameters in SelectionDAG::getLoad, ↵Justin Lebar1-115/+66
getStore, and friends. Summary: Instead, we take a single flags arg (a bitset). Also add a default 0 alignment, and change the order of arguments so the alignment comes before the flags. This greatly simplifies many callsites, and fixes a bug in AMDGPUISelLowering, wherein the order of the args to getLoad was inverted. It also greatly simplifies the process of adding another flag to getLoad. Reviewers: chandlerc, tstellarAMD Subscribers: jholewinski, arsenm, jyknight, dsanders, nemanjai, llvm-commits Differential Revision: http://reviews.llvm.org/D22249 llvm-svn: 275592
2016-07-15Rename AnalyzeBranch* to analyzeBranch*.Jacques Pienaar2-3/+3
Summary: NFC. Rename AnalyzeBranch/AnalyzeBranchPredicate to analyzeBranch/analyzeBranchPredicate to follow LLVM coding style and be consistent with TargetInstrInfo's analyzeCompare and analyzeSelect. Reviewers: tstellarAMD, mcrosier Subscribers: mcrosier, jholewinski, jfb, arsenm, dschuff, jyknight, dsanders, nemanjai Differential Revision: https://reviews.llvm.org/D22409 llvm-svn: 275564
2016-07-11Fix branch relaxation in 16-bit mode.Nirav Dave1-1/+2
Thread through MCSubtargetInfo to relaxInstruction function allowing relaxation to generate jumps with 16-bit sized immediates in 16-bit mode. This fixes PR22097. Reviewers: dwmw2, tstellarAMD, craig.topper, jyknight Subscribers: jfb, arsenm, jyknight, llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D20830 llvm-svn: 275068
2016-07-08Sparc: Avoid implicit iterator conversions, NFCDuncan P. N. Exon Smith1-3/+3
Remove the only implicit conversions from MachineInstrBundleIterator to MachineInstr* in the Sparc backend. llvm-svn: 274913
2016-07-08[Sparc] Leon errata fix passes.Chris Dewhurst8-173/+869
Errata fixes for various errata in different versions of the Leon variants of the Sparc 32 bit processor. The nature of the errata are listed in the comments preceding the errata fix passes. Relevant unit tests are implemented for each of these. Note: Running clang-format has changed a few other lines too, unrelated to the implemented errata fixes. These have been left in as this keeps the code formatting consistent. Differential Revision: http://reviews.llvm.org/D21960 llvm-svn: 274856
2016-07-02Use arrays or initializer lists to feed ArrayRefs instead of SmallVector ↵Benjamin Kramer1-7/+6
where possible. No functionality change intended. llvm-svn: 274431
2016-06-30CodeGen: Use MachineInstr& in TargetLowering, NFCDuncan P. N. Exon Smith2-32/+30
This is a mechanical change to make TargetLowering API take MachineInstr& (instead of MachineInstr*), since the argument is expected to be a valid MachineInstr. In one case, changed a parameter from MachineInstr* to MachineBasicBlock::iterator, since it was used as an insertion point. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. llvm-svn: 274287
2016-06-30Delete MCCodeGenInfo.Rafael Espindola1-25/+10
MC doesn't really care about CodeGen stuff, so this was just complicating target initialization. llvm-svn: 274258
2016-06-30CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith2-28/+25
This is mostly a mechanical change to make TargetInstrInfo API take MachineInstr& (instead of MachineInstr* or MachineBasicBlock::iterator) when the argument is expected to be a valid MachineInstr. This is a general API improvement. Although it would be possible to do this one function at a time, that would demand a quadratic amount of churn since many of these functions call each other. Instead I've done everything as a block and just updated what was necessary. This is mostly mechanical fixes: adding and removing `*` and `&` operators. The only non-mechanical change is to split ARMBaseInstrInfo::getOperandLatencyImpl out from ARMBaseInstrInfo::getOperandLatency. Previously, the latter took a `MachineInstr*` which it updated to the instruction bundle leader; now, the latter calls the former either with the same `MachineInstr&` or the bundle leader. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. Note: I updated WebAssembly, Lanai, and AVR (despite being off-by-default) since it turned out to be easy. I couldn't run tests for AVR since llc doesn't link with it turned on. llvm-svn: 274189
2016-06-27[Sparc] Atomics pass changes to make work with SparcV8 back-ends.Chris Dewhurst1-4/+2
This change reverts a "false" test that was placed to avoid regressions while the atomics pass was completed for the Sparc back-ends. llvm-svn: 273949
2016-06-27Use isPositionIndependent(). NFC.Rafael Espindola1-2/+2
llvm-svn: 273907
2016-06-27Use isPositionIndependent(). NFC.Rafael Espindola2-5/+3
llvm-svn: 273903
2016-06-27Last line of file missing on previous check-in.Chris Dewhurst1-0/+1
llvm-svn: 273878
2016-06-27[Sparc] Formatting and commenting changes per review.Chris Dewhurst2-185/+191
Differential Review: http://reviews.llvm.org/rL273108 llvm-svn: 273876
2016-06-27[sparc] Simplify slow and verbose string matching code to startswith_lower.Benjamin Kramer1-15/+10
No functionality change intended, found by cppcheck. PR28274. llvm-svn: 273857
2016-06-22Prune some includes from headers and sink some inline functionsReid Kleckner2-0/+2
MCSymbol.h shouldn't pull in MCAssembler.h, just MCFragment.h. MCLinkerOptimizationHint.h shouldn't need MCMachObjectWriter.h. The rest is fixing the fallout. llvm-svn: 273507
2016-06-22[SDAG] Remove FixedArgs parameter from CallLoweringInfo::setCalleeKrzysztof Parzyszek1-2/+2
The setCallee function will set the number of fixed arguments based on the size of the argument list. The FixedArgs parameter was often explicitly set to 0, leading to a lack of consistent value for non- vararg functions. Differential Revision: http://reviews.llvm.org/D20376 llvm-svn: 273403
2016-06-19[SPARC] Additional condition required for DelaySlot fixing erratum in ↵Chris Dewhurst1-0/+7
revision r273108. llvm-svn: 273111
2016-06-19[SPARC] Fixes for hardware errata on LEON processor.Chris Dewhurst9-1/+449
Passes to fix three hardware errata that appear on some LEON processor variants. The instructions FSMULD, FMULS and FDIVS do not work as expected on some LEON processors. This change allows those instructions to be substituted for alternatives instruction sequences that are known to work. These passes only run when selected individually, or as part of a processor defintion. They are not included in general SPARC processor compilations for non-LEON processors or for those LEON processors that do not have these hardware errata. llvm-svn: 273108
2016-06-17Support expanding partial-word cmpxchg to full-word cmpxchg in AtomicExpandPass.James Y Knight1-0/+2
Many CPUs only have the ability to do a 4-byte cmpxchg (or ll/sc), not 1 or 2-byte. For those, you need to mask and shift the 1 or 2 byte values appropriately to use the 4-byte instruction. This change adds support for cmpxchg-based instruction sets (only SPARC, in LLVM). The support can be extended for LL/SC-based PPC and MIPS in the future, supplanting the ISel expansions those architectures currently use. Tests added for the IR transform and SPARCv9. Differential Revision: http://reviews.llvm.org/D21029 llvm-svn: 273025
2016-06-12Pass DebugLoc and SDLoc by const ref.Benjamin Kramer5-94/+66
This used to be free, copying and moving DebugLocs became expensive after the metadata rewrite. Passing by reference eliminates a ton of track/untrack operations. No functionality change intended. llvm-svn: 272512
2016-06-01[Sparc] Allow passing of empty structs.Chris Dewhurst1-11/+21
Passing an empty struct as a function call argument is now supported. unit tests for various scenarios added. llvm-svn: 271374
2016-05-27[sparc] Simplify a slow and verbose way of checking if a string starts with ↵Benjamin Kramer1-6/+4
"ld". PR27904. llvm-svn: 271016
2016-05-27Apply clang-tidy's misc-static-assert where it makes sense.Benjamin Kramer1-1/+2
Also fold conditions into assert(0) where it makes sense. No functional change intended. llvm-svn: 270982
2016-05-27[sparc] Remove some unused (and undefined) declarations.Benjamin Kramer4-14/+2
No functionality change. llvm-svn: 270981
2016-05-27[sparc] Move LEON passes into llvm namespace.Benjamin Kramer2-4/+6
Also give them library visiblity while there. llvm-svn: 270979
2016-05-26[Sparc] Extend the assembler printing support for Sparc back-end.Chris Dewhurst1-0/+4
Allows display of floating-point registers and display of assembler meta-data output. llvm-svn: 270829
2016-05-23[SPARC] Fix 8 and 16-bit atomic load and store.James Y Knight2-14/+22
They were accidentally using the 32-bit load/store instruction for 8/16-bit operations, due to incorrect patterns (8/16-bit cmpxchg and atomicrmw will be fixed in subsequent changes) llvm-svn: 270486
2016-05-23[Sparc] LEON erratum fix - Delay Slot Filler modification.Chris Dewhurst1-0/+9
This code should have been with the previous check-in (r270417) and prevents the DelaySlotFiller pass being utilized in functions where the erratum fix has been applied as this will break the run-time code. llvm-svn: 270418
2016-05-23[Sparc][LEON] LEON Erratum fix. Insert NOP after LD or LDF instruction.Chris Dewhurst10-9/+152
Due to an erratum in some versions of LEON, we must insert a NOP after any LD or LDF instruction to ensure the processor has time to load the value correctly before using it. This pass will implement that erratum fix. The code will have no effect for other Sparc, but non-LEON processors. Differential Review: http://reviews.llvm.org/D20353 llvm-svn: 270417
2016-05-23Test commitJacob Baungard Hansen1-1/+0
llvm-svn: 270414
2016-05-20SparcISelLowering.cpp: Add missing StringSwitch.hNAKAMURA Takumi1-0/+1
llvm-svn: 270200
2016-05-20[Sparc] Implement getRegisterByName.Chris Dewhurst2-0/+24
Allows Sparc registers to be specifically referred to in inline assembly. llvm-svn: 270198
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