riscv-gnu-toolchain/llvm.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2026-01-13	[CodeGen][InlineSpiller] Add SubReg argument to loadRegFromStackSlot for subr...	Christudasan Devadasan	3	-7/+11
2026-01-12	[RISCV] Add the missing SEW search table field to vector FMA instructions (#1...	Min-Yih Hsu	1	-1/+1
2026-01-13	[RISCV] Adjust base cost for Xqcilo loads/stores in RISCVMakeCompressible (#1...	Sudharsan Veeravalli	1	-7/+38
2026-01-13	[RISCV] Use LD_RV32/SD_RV32 for spills and reloads when Zilsd is enabled (#15...	Sudharsan Veeravalli	1	-6/+18
2026-01-12	[llvm][RISCV] Suppress unused `IsMulH` warning. (#175653)	Chenguang Wang	1	-2/+3
2026-01-12	[RISCV] Add isel patterns for ANDN/ORN/XNOR with P+Zbb. (#175384)	Craig Topper	1	-0/+15
2026-01-12	[llvm][RISCV] Support rounding mulh for P extension codegen (#171593)	Brandon Wu	2	-13/+63
2026-01-12	[RISCV] Detect QC_E_ADDAI and fold in RISCVMergeBaseOffset (#175496)	Sudharsan Veeravalli	1	-1/+2
2026-01-12	[RISCV] Fix ReplaceNodeResults of Intrinsic::experimental_cttz_elts for RV32 ...	Alex Bradbury	1	-2/+1
2026-01-12	[RISCV][llvm] Support logical comparison codegen for P extension (#174626)	Brandon Wu	2	-0/+37
2026-01-12	[RISCV] Schedule RVV instructions with compatible vtype/vl first	Pengcheng Wang	3	-5/+120
2026-01-12	[RISCV][NFC] Add RISCVVSETVLIInfoAnalysis	Pengcheng Wang	6	-1030/+1116
2026-01-12	[RISCV] Add a custom pre-ra scheduler	Pengcheng Wang	4	-1/+158
2026-01-12	[RISCV] Add support for QC.E.LI in RISCVMergeBaseOffset (#175310)	Sudharsan Veeravalli	1	-38/+53
2026-01-11	[TargetLowering] Change the `softPromoteHalfType` default to `true` (#175149)	Trevor Gross	1	-2/+0
2026-01-10	[RISCV] Use static arrays+ArrayRef instead of SmallVector to select P extensi...	Craig Topper	1	-3/+5
2026-01-10	[RISCV] Mark Xqccmp as not experimental (#175066)	Sam Elliott	1	-3/+2
2026-01-09	[RISCV] Try to disassemble 48-bit and larger instructions as 32-bit instructi...	Craig Topper	1	-6/+12
2026-01-09	[RISCV] Support i32 (S/U)(ADD/SUB)SAT for rv32ip. (#173693)	Craig Topper	2	-8/+15
2026-01-09	[RISCV] Prevent P extension from creating unaligned scalar load/store insruct...	Craig Topper	1	-1/+1
2026-01-09	[RISCV] Merge multiple QC_EXTU patterns using ImmLeaf and SDNodeXForm. (#175119)	Craig Topper	1	-7/+16
2026-01-10	[RISCV][llvm] Support frame index in zilsd optimizer (#174073)	Brandon Wu	2	-20/+36
2026-01-09	[RISCV] Add support for Zibi experimental extension in RISCVRedundantCopyElim...	Boyao Wang	1	-6/+7
2026-01-08	[TableGen] Support RegClassByHwMode in CompressPat	Alexander Richardson	1	-0/+1
2026-01-08	[RISCV] Mark More Relocs as Relaxable (#151422)	Sam Elliott	2	-17/+29
2026-01-08	[RISCV] Bail out of combineNarrowableShiftedLoad for types other than scalar ...	Alex Bradbury	1	-2/+4
2026-01-08	[RISC-V][Mach-O] Print immediate operands in hexadecimal format. (#174505)	Francesco Petrogalli	2	-1/+19
2026-01-08	[RISCV][llvm] Support div/rem codegen for P extension (#174801)	Brandon Wu	1	-0/+3
2026-01-08	[RISCV][llvm] Support mul codegen for P extension (#174793)	Brandon Wu	1	-0/+14
2026-01-08	[RISCV][llvm] Support bitwise operation for XLEN fixed vectors (#174598)	Brandon Wu	1	-0/+18
2026-01-08	[RISCV] Generate Xqcilsm multi-word load/store instructions for three or more...	Sudharsan Veeravalli	1	-17/+217
2026-01-08	[RISCV] Add missing comment at end of let scope in RISCVInstrInfoXAndes.td. NFC.	Jim Lin	1	-7/+9
2026-01-08	[RISCV] Indent body of let scopes in RISCVInstrInfoXAndes.td. NFC.	Jim Lin	1	-120/+118
2026-01-08	[RISCV] Fold (fma (splat (fneg X)), Y, Z) -> (fma (fneg (splat X)), Y, Z) (#1...	Liao Chunyu	1	-1/+17
2026-01-08	[RISC-V] Ensure MCTargetStreamer is initialized. (#174800)	Francesco Petrogalli	2	-1/+3
2026-01-07	[RISCV] Improve cost modeling of RISCVTTIImpl::getConstantPoolLoadCost() (#17...	Ryan Buchner	2	-2/+26
2026-01-08	[RISCV] Add support for XAndesPerf branch on immediate in RISCVRedundantCopyE...	Jim Lin	1	-5/+9
2026-01-08	[RISC-V][ELF] Move emitNoteGnuPropertySection to RISCVTargetELFStreamer. [NFC...	Francesco Petrogalli	5	-44/+46
2026-01-07	[RISCV] Use ZeroOrNegativeOneBooleanContent for RVV to match P extension. (#1...	Craig Topper	1	-1/+1
2026-01-06	[RISC-V][Mach-O] Implement and select the RISCVMachOTargetObjectFile. (#174677)	Francesco Petrogalli	2	-1/+12
2026-01-07	[RISCV] Fix typo from 6e86037. NFC (#174679)	Sudharsan Veeravalli	1	-1/+1
2026-01-06	[RISCV] Add computeKnownBits for CLSW. (#174636)	Craig Topper	1	-0/+15
2026-01-07	[RISCV] Improve load/store pairing for Xqcilsm instructions in RISCVLoadStore...	Sudharsan Veeravalli	1	-4/+14
2026-01-06	[RISCV] Add SimplifyDemandedBits and hasAllNBitUsers support for CLSW. (#174542)	Craig Topper	3	-0/+3
2026-01-06	[RISCV] Don't generate QC.SWMI pair if the start reg is X0 (#174532)	Sudharsan Veeravalli	1	-1/+1
2026-01-06	[IR] Split vector.splice into vector.splice.left and vector.splice.right (#17...	Luke Lau	1	-14/+18
2026-01-06	[RISCV] Add support for Xqcibi branch on immediate in RISCVRedundantCopyElimi...	Sudharsan Veeravalli	1	-26/+76
2026-01-05	[RISCV,CMake] Add BinaryFormat dependency after #141682	Fangrui Song	1	-0/+1
2026-01-05	[RISCV] Add basic Mach-O triple support. (#141682)	Francesco Petrogalli	8	-1/+115
2026-01-05	[llvm][RISCV] Support fma codegen for zvfbfa (#172949)	Brandon Wu	3	-35/+95