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path: root/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
AgeCommit message (Expand)AuthorFilesLines
2024-10-01[RISCV][GISel] Add RISCVPassConfig::getCSEConfig() to match other targets. (#...Craig Topper1-0/+7
2024-10-01[RISCV] Enable load clustering by default (#73789)Alex Bradbury1-1/+1
2024-09-20Revert "[RISCV][GISEL] Introduce the RISCVPostLegalizerLowering pass (#108991)"Michael Maitland1-2/+0
2024-09-19[RISCV] Add additional fence for amocas when required by recent ABI change (#...Alex Bradbury1-0/+1
2024-09-17[RISCV][GISEL] Introduce the RISCVPostLegalizerLowering pass (#108991)Michael Maitland1-0/+2
2024-08-17[LSR] Split the -lsr-term-fold transformation into it's own pass (#104234)Philip Reames1-0/+1
2024-08-08[RISCV] Insert simple landing pad before indirect jumps for Zicfilp. (#91860)Yeting Kuo1-0/+1
2024-08-06[RISCV] Insert simple landing pad for taken address labels. (#91855)Yeting Kuo1-0/+1
2024-07-22[CodeGen] change prototype of regalloc filter function (#93525)Christudasan Devadasan1-2/+4
2024-07-11[RISCV] Convert AVLs with vlenb to VLMAX where possible (#97800)Luke Lau1-2/+2
2024-07-02[RISCV][LoopIdiomVectorize] Support VP intrinsics in LoopIdiomVectorize (#94082)Min-Yih Hsu1-0/+9
2024-07-02[RISCV] Move Machine Copy Propagation Pass before Branch relaxation pass (#97...Yunzezhu941-3/+2
2024-06-04Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)paperchalice1-1/+1
2024-06-02Revert "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94146)paperchalice1-1/+1
2024-06-02[NewPM][CodeGen] Port selection dag isel to new pass manager (#83567)paperchalice1-1/+1
2024-05-29[RISCV] Merge RISCVCoalesceVSETVLI back into RISCVInsertVSETVLI (#92869)Luke Lau1-3/+0
2024-05-21[RISCV] Support postRA vsetvl insertion pass (#70549)Piyou Chen1-4/+15
2024-05-16[RISCV] Defer creating RISCVInsertVSETVLI to avoid leak with -stop-after (#92...Luke Lau1-2/+2
2024-05-15[RISCV] Move RISCVInsertVSETVLI to after phi elimination (#91440)Luke Lau1-1/+8
2024-05-10[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)Luke Lau1-1/+1
2024-05-07[RISCV] Move RISCVDeadRegisterDefinitions to post vector regalloc (#90636)Luke Lau1-3/+6
2024-04-25Reapply "[RISCV] Separate doLocalPostpass into new pass and move to post vect...Luke Lau1-0/+3
2024-04-24Revert "[RISCV] Separate doLocalPostpass into new pass and move to post vecto...Luke Lau1-3/+0
2024-04-24[RISCV] Separate doLocalPostpass into new pass and move to post vector regall...Luke Lau1-0/+3
2024-04-24[RISCV] Remove -riscv-split-regalloc flag (#89715)Luke Lau1-11/+3
2024-03-07[RISCV][NFC] Add helpers for RVV register classesWang Pengcheng1-15/+1
2024-02-26[CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add suppor...Jack Styles1-9/+1
2024-02-25[CodeGen] Port AtomicExpand to new Pass Manager (#71220)Rishabh Bali1-1/+1
2024-02-22[RISCV] Enable -riscv-enable-sink-fold by default. (#82026)Craig Topper1-1/+1
2024-02-13[RISCV] Enable the TypePromotion pass from AArch64/ARM.Craig Topper1-0/+7
2024-02-07[RISCV] Remove unused variable 'ST' in RISCVTargetMachine.cpp (NFC)Jie Fu1-1/+0
2024-02-07[Sched] Add MacroFusion mutation if fusions are not empty (#72227)Wang Pengcheng1-17/+0
2024-01-25[RISCV] Use TableGen-based macro fusion (#72224)Wang Pengcheng1-5/+8
2024-01-16[RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777)Wang Pengcheng1-3/+13
2024-01-16[MachineScheduler] Add option to control reordering for store/load clustering...Alex Bradbury1-1/+2
2023-12-08[RISCV][NFC] Use raw_svector_ostream to construct key of SubtargetMap (#72964)Wang Pengcheng1-7/+2
2023-12-07[RISCV] Use Triple::isRISCV64(). NFCCraig Topper1-1/+1
2023-11-30[RISCV] default enable splitting regalloc between RVV and other (#72950)Piyou Chen1-1/+1
2023-11-29[RISCV] Support load clustering in the MachineScheduler (off by default) (#73...Alex Bradbury1-3/+12
2023-11-16[RISCV] Split regalloc between RVV and other (#72096)Piyou Chen1-0/+108
2023-11-10[RISCV] Enable LoopDataPrefetch pass (#66201)Wang Pengcheng1-0/+9
2023-11-02[RISCV] Implement cross basic block VXRM write insertion. (#70382)Craig Topper1-0/+2
2023-10-30[RISCV] Begin moving post-isel vector peepholes to a MF pass (#70342)Luke Lau1-0/+4
2023-10-25[RISCV] Add an experimental pseudoinstruction to represent a rematerializable...Craig Topper1-0/+3
2023-10-19[RISCV] Replace PostRAScheduler with PostMachineScheduler (#68696)Wang Pengcheng1-0/+2
2023-10-07[RISCV] Add sink-and-fold support for RISC-V. (#67602)Craig Topper1-1/+8
2023-09-22[RISCV][GISel] Add a post legalizer combiner and enable a couple comb… (#67...Craig Topper1-0/+7
2023-09-20[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose ret...Yingwei Zheng1-0/+11
2023-09-18[RISCV][GISel] Add initial pre-legalizer combiners copying from AArch64.Craig Topper1-0/+11
2023-09-14[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#6...Arthur Eubanks1-7/+9
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