| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2026-01-12 | [llvm][RISCV] Suppress unused `IsMulH` warning. (#175653) | Chenguang Wang | 1 | -2/+3 |
| 2026-01-12 | [llvm][RISCV] Support rounding mulh for P extension codegen (#171593) | Brandon Wu | 1 | -13/+50 |
| 2026-01-12 | [RISCV] Fix ReplaceNodeResults of Intrinsic::experimental_cttz_elts for RV32 ... | Alex Bradbury | 1 | -2/+1 |
| 2026-01-12 | [RISCV][llvm] Support logical comparison codegen for P extension (#174626) | Brandon Wu | 1 | -0/+6 |
| 2026-01-10 | [RISCV] Use static arrays+ArrayRef instead of SmallVector to select P extensi... | Craig Topper | 1 | -3/+5 |
| 2026-01-09 | [RISCV] Support i32 (S/U)(ADD/SUB)SAT for rv32ip. (#173693) | Craig Topper | 1 | -8/+11 |
| 2026-01-09 | [RISCV] Prevent P extension from creating unaligned scalar load/store insruct... | Craig Topper | 1 | -1/+1 |
| 2026-01-08 | [RISCV] Bail out of combineNarrowableShiftedLoad for types other than scalar ... | Alex Bradbury | 1 | -2/+4 |
| 2026-01-08 | [RISCV][llvm] Support div/rem codegen for P extension (#174801) | Brandon Wu | 1 | -0/+3 |
| 2026-01-08 | [RISCV] Fold (fma (splat (fneg X)), Y, Z) -> (fma (fneg (splat X)), Y, Z) (#1... | Liao Chunyu | 1 | -1/+17 |
| 2026-01-07 | [RISCV] Use ZeroOrNegativeOneBooleanContent for RVV to match P extension. (#1... | Craig Topper | 1 | -1/+1 |
| 2026-01-06 | [RISCV] Add computeKnownBits for CLSW. (#174636) | Craig Topper | 1 | -0/+15 |
| 2026-01-06 | [RISCV] Add SimplifyDemandedBits and hasAllNBitUsers support for CLSW. (#174542) | Craig Topper | 1 | -0/+1 |
| 2026-01-06 | [IR] Split vector.splice into vector.splice.left and vector.splice.right (#17... | Luke Lau | 1 | -14/+18 |
| 2026-01-05 | [llvm][RISCV] Support fma codegen for zvfbfa (#172949) | Brandon Wu | 1 | -7/+15 |
| 2026-01-04 | [RISCV][SelectionDAG] Add a ISD::CTLS node for count leading redundant sign b... | Craig Topper | 1 | -4/+23 |
| 2026-01-03 | [RISCV] Support i32 SSHLAT for rv32ip. (#173687) | Craig Topper | 1 | -1/+7 |
| 2025-12-28 | [CodeGen] Fix EVT::changeVectorElementType assertion on simple-to-extended fa... | Islam Imad | 1 | -3/+4 |
| 2025-12-25 | [RISCV] Use TargetConstant for intrinsic IDs (#173517) | Sudharsan Veeravalli | 1 | -5/+6 |
| 2025-12-23 | [RISCV] Support srx/slx for P extension. (#173225) | Craig Topper | 1 | -0/+3 |
| 2025-12-21 | [RISCV] Use legally typed splat during vmv_v_v splat(x) -> vmv_v_x (#173154) | Hongyu Chen | 1 | -1/+1 |
| 2025-12-21 | [RISCV] Introduce new AND combine to expose additional load narrowing opportu... | Alex Bradbury | 1 | -1/+43 |
| 2025-12-19 | [RISCV] Handle codegen for Big Endian (#172668) | Djordje Todorovic | 1 | -14/+64 |
| 2025-12-19 | [RISCV][llvm] Remove custom legalization of fixed-length vector SPLAT_VECTOR ... | Brandon Wu | 1 | -5/+5 |
| 2025-12-18 | [RISCV] Rename -enable-p-ext-codegen -riscv-enable-p-ext-simd-codegen. (#172790) | Craig Topper | 1 | -9/+9 |
| 2025-12-17 | [RISCV] Extract vector from passthru when combining tuple_extract+vlseg. (#17... | Craig Topper | 1 | -1/+8 |
| 2025-12-18 | [RISCV][llvm] Support fminimum, fmaximum, fminnum, fmaxnum, fminimumnum, fmax... | Brandon Wu | 1 | -9/+9 |
| 2025-12-17 | fix `llvm.fma.f16` double rounding issue when there is no native support (#17... | Folkert de Vries | 1 | -0/+9 |
| 2025-12-16 | [CodeGen] expand-fp: Change frem expansion criterion (#158285) | Frederik Harwath | 1 | -3/+5 |
| 2025-12-15 | [llvm][RISCV] Support mulh for P extension codegen (#171581) | Brandon Wu | 1 | -30/+47 |
| 2025-12-14 | [RISCV] Custom legalize i32 saddo/ssubo on RV64 to return a sign extended val... | Craig Topper | 1 | -22/+29 |
| 2025-12-11 | [RISCV][llvm] Support PSRA, PSRAI, PSRL, PSRLI codegen for P extension (#171460) | Brandon Wu | 1 | -15/+14 |
| 2025-12-10 | [RISCV] Add Xsfmm vlte and vste intrinsics to getTgtMemIntrinsics. (#171747) | Craig Topper | 1 | -0/+54 |
| 2025-12-10 | [RISCV] Reduce code duplication. NFC (#171577) | Craig Topper | 1 | -11/+6 |
| 2025-12-09 | [RISCV] Add fractional LMUL register classes for inline assembly. (#171278) | Craig Topper | 1 | -24/+27 |
| 2025-12-09 | [RISCV] Use VM and VMNoV0 for "vr" and "vd" inline asm constraints with mask ... | Craig Topper | 1 | -15/+17 |
| 2025-12-09 | [IR][RISCV] Remove @llvm.experimental.vp.splat (#171084) | Luke Lau | 1 | -53/+5 |
| 2025-12-08 | [RISCV] Remove unnecesary override of getVectorTypeBreakdownForCallingConv. N... | Craig Topper | 1 | -12/+1 |
| 2025-12-07 | [RISCV] Update P extension to the 018 version of the spec. (#170399) | Craig Topper | 1 | -25/+3 |
| 2025-12-05 | [RISCV][llvm] Support VFADD, VFSUB, VFMUL codegen for Zvfbfa (#170612) | Brandon Wu | 1 | -5/+40 |
| 2025-12-05 | [RISCV][llvm] Support PSLL codegen for P extension (#170074) | Brandon Wu | 1 | -0/+13 |
| 2025-12-04 | [RISCV] Combine vmerge_vl allones -> vmv_v_v, vmv_v_v splat(x) -> vmv_v_x (#1... | Luke Lau | 1 | -0/+38 |
| 2025-12-04 | [RISCV][GISel] Support select G_EXTRACT_SUBVECTOR (#169789) | Jianjian Guan | 1 | -0/+2 |
| 2025-12-02 | [NFC] Refactor TargetLowering::getTgtMemIntrinsic to take CallBase parameter ... | Robert Imschweiler | 1 | -1/+1 |
| 2025-12-01 | [RISCV] Rename SFB Base Feature (#169607) | Sam Elliott | 1 | -4/+4 |
| 2025-12-01 | [SelectionDAG] Add SelectionDAG::getTypeSize. NFC (#169764) | Luke Lau | 1 | -6/+2 |
| 2025-12-01 | [RISCV][llvm] Correct shamt in P extension EXTRACT_VECTOR_ELT lowering (#169823) | Brandon Wu | 1 | -1/+1 |
| 2025-12-01 | [RISCV][ISelLowering] Use Zicond for FP selects on Zfinx/Zdinx (#169299) | fennecJ | 1 | -0/+44 |
| 2025-11-30 | [TTI][RISCV] Add cost modelling for intrinsic vp.load.ff (#169890) | Shih-Po Hung | 1 | -0/+16 |
| 2025-11-26 | [llvm][RISCV] Support P Extension CodeGen (#167895) | Brandon Wu | 1 | -0/+1 |
