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path: root/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
AgeCommit message (Expand)AuthorFilesLines
2025-01-07[RISCV] Add Qualcomm uC Xqcicm (Conditional Move) extension (#121752)quic_hchandel1-0/+5
2025-01-03[RISCV] Add Qualcomm uC Xqcicli (Conditional Load Immediate) extension (#121292)Sudharsan Veeravalli1-0/+3
2024-12-29[RISCV] Add Qualcomm uC Xqciac (Load-Store Adress calculation) extension (#12...quic_hchandel1-0/+6
2024-12-14[RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (#119823)Sudharsan Veeravalli1-0/+2
2024-12-12[RISCV] Add Qualcomm uC Xqcics(Conditional Select) extension (#119504)quic_hchandel1-0/+2
2024-12-01[RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (#118113)Sudharsan Veeravalli1-0/+2
2024-11-29[RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store) extension (#117987)Sudharsan Veeravalli1-0/+2
2024-11-28[RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169)Sudharsan Veeravalli1-0/+2
2024-11-08[RISCV] Only allow 5 bit shift amounts in disassembler for RV32. (#115432)Craig Topper1-0/+21
2024-10-06[RISCV] Only disassemble fcvtmod.w.d if the rounding mode is rtz. (#111308)Craig Topper1-0/+10
2024-10-01[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)Craig Topper1-0/+13
2024-09-26[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)Craig Topper1-0/+13
2024-09-10[RISCV] Fix fneg.d/fabs.d aliasing handling for Zdinx. Add missing fmv.s/d al...Craig Topper1-2/+7
2024-07-11[RISCV] Add QingKe "XW" compressed opcode extension (#97925)R1-0/+3
2024-04-29[RISCV] Support instruction sizes up to 176-bits in disassembler. (#90371)Craig Topper1-5/+37
2024-04-26[RISCV] Split RISCVDisassembler::getInstruction into a 16-bit and 32-bit vers...Craig Topper1-99/+119
2024-04-26[RISCV] Fix off by 1 typo in decodeVMaskReg. NFCCraig Topper1-2/+2
2024-04-26[RISCV] Consistently use uint32_t in Disassembler decode functions. NFCCraig Topper1-6/+6
2024-04-19[RISCV] Rename FeatureRVE to FeatureStdExtE. NFC (#89174)Craig Topper1-1/+1
2024-03-13[RISCV] Add back SiFive's cdiscard.d.l1, cflush.d.l1, and cease instructions....Craig Topper1-0/+8
2024-02-06[RISCV][NFC] Use maybe_unused instead of casting to void to fix unused variab...Yeting Kuo1-10/+10
2024-01-10[RISCV] Re-implement Zacas MC layer support to make it usable for CodeGen. (#...Craig Topper1-0/+4
2024-01-09[RISCV] Refactor GPRF64 register class to make it usable for Zacas. (#77408)Craig Topper1-1/+1
2023-12-30[RISCV] Add MC layer support for Zicfiss. (#66043)Yeting Kuo1-0/+27
2023-12-28[RISCV] Remove XSfcie extension.Craig Topper1-2/+0
2023-12-27[RISCV] Update DecoderMethod and MCOperandPredicate of spimm. (#76061)Yeting Kuo1-2/+0
2023-11-16[RISCV][MC] MC layer support for xcvmem and xcvelw extensionsLiaoChunyu1-0/+16
2023-11-03[RISCV] Support Xsfvfnrclipxfqf extensions (#68297)Brandon Wu1-0/+3
2023-11-03[RISCV] Support Xsfvfwmaccqqq extensions (#68296)Brandon Wu1-0/+3
2023-10-31[RISCV][NFC] Simplify vector register decoding methods (#70423)flyingcat1-20/+6
2023-10-20[RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (#68295)Brandon Wu1-0/+6
2023-08-19[RISCV] Rename Ventana DecoderNamespace to XVentana for matching other extens...Jim Lin1-1/+1
2023-07-30[RISCV] Rename XTHead DecoderNamespaces to match their extension names includ...Craig Topper1-11/+11
2023-07-30[RISCV] Rename DecoderNamespace for XCVsimd to be consistent with other XCV e...Craig Topper1-1/+1
2023-07-28 [RISCV] Add support for XCVbi extension in CV32E40Pmelonedo1-0/+2
2023-07-28Revert "[RISCV] Add support for XCVbi extension in CV32E40P"melonedo1-2/+0
2023-07-28[RISCV] Add support for XCVbi extension in CV32E40Pmelonedo1-0/+2
2023-07-28[RISCV] Add support for XCVsimd extension in CV32E40Pmelonedo1-0/+2
2023-07-28[RISCV] Add support for XCValu extension in CV32E40PQihan Cai1-0/+2
2023-06-26[RISCV] Add support for custom instructions for Sifive S76.Garvit Gupta1-0/+2
2023-06-21[RISCV] Add support for XCVmac extension in CV32E40PQihan Cai1-0/+2
2023-06-19[RISCV] Add support for XCVbitmanip extension in CV32E40Pmelonedo1-0/+3
2023-05-25[RISCV][NFC] Simplify decoding code of disassemblerwangpc1-146/+72
2023-05-16[RISCV] Rework how implied SP operands work in the disassembler. NFCCraig Topper1-22/+20
2023-05-08[RISCV] Add MC support of RISCV zcmp ExtensionWuXinlong1-0/+42
2023-05-05[RISCV] Add DecoderNamespace to Zcmt instructions.Craig Topper1-0/+8
2023-05-04[RISCV] Directly create MCOperands from addImplySP in Disassembler. NFCCraig Topper1-7/+6
2023-04-09[RISCV] Support assembler and dis-assembler for VCIX extension.Nelson Chu1-0/+7
2023-03-27[RISCV] Replace RISCV -> RISC-V in comments. NFCCraig Topper1-1/+1
2023-03-23[RISCV][MC] Add support for RV64EJob Noorman1-2/+2
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