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path: root/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
AgeCommit message (Expand)AuthorFilesLines
2025-06-28[PowerPC] Use range-based for loops (NFC) (#146221)Kazu Hirata1-10/+10
2025-03-18[PowerPC] Avoid repeated hash lookups (NFC) (#131724)Kazu Hirata1-5/+6
2025-03-16[PowerPC] Avoid repeated hash lookups (NFC) (#131498)Kazu Hirata1-9/+6
2025-02-20[FrameLowering] Use MCRegister instead of Register in CalleeSavedInfo. NFC (#...Craig Topper1-6/+6
2025-02-18[PowerPC] Used named subreg indices instead of hardcoded numbers. NFC (#127671)Craig Topper1-2/+2
2025-02-18[PowerPC] Use MCRegister. NFCCraig Topper1-5/+5
2025-01-22[PowerPC] Fix saving of Link Register when using ROP Protect (#123101)Stefan Pintilie1-3/+6
2025-01-14[llvm] Mark scavenging spill-slots as *spilled* stack objects. (#122673)Guy David1-3/+2
2024-11-04[PowerPC] Utilize getReservedRegs to find asm clobberable registers. (#107863)zhijian lin1-0/+8
2024-10-18[llvm] Consistently respect `naked` fn attribute in `TargetFrameLowering::has...Alex Rønne Petersen1-3/+3
2024-09-03[PowerPC] Use DenseMap::operator[] (NFC) (#107044)Kazu Hirata1-2/+1
2024-08-07[PPC][AIX] Save/restore r31 when using base pointer (#100182)Zaara Syeda1-2/+12
2024-07-19CodeGen: Avoid some references to MachineFunction's getMMI (#99652)Matt Arsenault1-4/+2
2024-06-20[PowerPC] use r1 as the frame pointer when there is dynamic allocaChen Zheng1-1/+4
2024-06-07[PowerPC] return correct frame address for frameaddress intrinsicChen Zheng1-1/+2
2024-05-07[PowerPC] Spill non-volatile registers required for traceback table (#71115)Maryam Moghadas1-0/+59
2024-04-15[NFC] Refactor looping over recomputeLiveIns into function (#88040)Kai Nacke1-9/+2
2024-03-21[PowerPC] Clang format (NFC).Christudasan Devadasan1-1/+1
2024-03-02[PowerPC] provide CFI for ELF32 to unwind cr2, cr3, cr4 (#83098)George Koehler1-6/+0
2024-01-30Refactor recomputeLiveIns to converge on added MachineBasicBlocks (#79940)Oskar Wirga1-4/+9
2024-01-26Revert "Refactor recomputeLiveIns to operate on whole CFG (#79498)"Nikita Popov1-2/+4
2024-01-26Refactor recomputeLiveIns to operate on whole CFG (#79498)Oskar Wirga1-4/+2
2023-12-01[llvm][PowerPC] Correct handling of spill slots for SPE when EXPENSIVE_CHECKS...David Spickett1-16/+8
2023-11-08[RegScavenger] Simplify state tracking for backwards scavenging (#71202)Jay Foad1-1/+1
2023-09-08[PEI][PowerPC] Fix false alarm of stack size limit (#65559)bzEq1-0/+14
2023-07-23[PowerPC/SPE] powerpcspe load and store instruction hasKishan Parmar1-4/+6
2023-06-21PowerPC/SPE: Add phony registers for high halves of SPE SuperRegsKishan Parmar1-3/+30
2023-05-23[PowerPC] Avoid RegScavenger::forward in PPCFrameLoweringJay Foad1-12/+12
2023-04-15[Target] Use range-based for loops (NFC)Kazu Hirata1-2/+1
2022-12-17[CodeGen] Additional Register argument to storeRegToStackSlot/loadRegFromStac...Christudasan Devadasan1-3/+4
2022-11-22[PowerPC] store the LR before stack update for big offsets.Chen Zheng1-2/+5
2022-11-14[PowerPC] make expensive mflr be away from its user in the function prologueChen Zheng1-10/+26
2022-09-08[llvm] Use std::size instead of llvm::array_lengthofJoe Loser1-4/+4
2022-06-06[PowerPC] Support huge frame size for PPC64Kai Luo1-21/+5
2022-06-05[llvm] Convert for_each to range-based for loops (NFC)Kazu Hirata1-2/+2
2022-03-16Cleanup codegen includesserge-sans-paille1-1/+2
2022-03-15[PowerPC][P10] Add Vector pair calling conventionStefan Pintilie1-0/+9
2022-03-10Revert "Cleanup codegen includes"Nico Weber1-2/+1
2022-03-10Cleanup codegen includesserge-sans-paille1-1/+2
2022-01-26Revert "Rename llvm::array_lengthof into llvm::size to match std::size from C...Benjamin Kramer1-4/+4
2022-01-26Rename llvm::array_lengthof into llvm::size to match std::size from C++17serge-sans-paille1-4/+4
2022-01-19[NFC] Use Register instead of unsignedJim Lin1-6/+6
2022-01-05[PowerPC] Add support for ROP protection for 32 bit.Stefan Pintilie1-2/+4
2021-11-22[llvm] Use range-based for loops (NFC)Kazu Hirata1-3/+2
2021-11-21[llvm] Use range-based for loops (NFC)Kazu Hirata1-18/+18
2021-08-23[PowerPC] Use int64_t to represent stack object offset and frame sizeKai Luo1-22/+22
2021-06-09[PowerPC] Make sure the first probe is full size or is the last probe when st...Kai Luo1-178/+187
2021-05-13[PowerPC] Add ROP Protection to prologue and epilogueStefan Pintilie1-5/+51
2021-05-11[PowerPC][Bug] Fix Bug in Stack Frame Update CodeStefan Pintilie1-0/+22
2021-04-20[PowerPC] Use mtvsrdd to put callee-saved GPR into VSRQiu Chaofan1-13/+86
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