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2026-01-13[CodeGen][InlineSpiller] Add SubReg argument to loadRegFromStackSlot for subr...Christudasan Devadasan2-2/+2
2026-01-11[TargetLowering] Change the `softPromoteHalfType` default to `true` (#175149)Trevor Gross1-1/+0
2026-01-09[CodeGen] Generalise Hexagon flags for memop inline thresholds (#172829)Ties Stuij1-31/+6
2026-01-05[NFC][Hexagon] Fix unused variable warning (#174466)Aiden Grossman1-2/+3
2026-01-05Honor alignment for HVX masked loads/stores (incl. loops) (#174419)Fateme Hosseini1-41/+311
2025-12-31[Hexagon] TableGen-erate SDNode descriptions (#168272)Sergei Barannikov6-162/+143
2025-12-21[Hexagon] Silence warnings with MSVCAlexandre Ganea1-2/+3
2025-12-16[CodeGen] expand-fp: Change frem expansion criterion (#158285)Frederik Harwath1-5/+5
2025-12-11[Hexagon] Add HVX patterns for vector arithmetic (#170704)Fateme Hosseini2-0/+65
2025-12-11[Hexagon] Fix HWBF16 PatLeaf type (#170560)Fateme Hosseini2-1/+13
2025-12-11[SCEVExp] Get DL from SE, strip constructor arg (NFC) (#171823)Ramkumar Ramachandra1-1/+1
2025-12-10Revert "[Hexagon] Passes for widening vector operations and shuffle o… (#17...Brian Cain14-2741/+17
2025-12-09[ADT] BitVector: give `subsetOf(RHS)` name to `!test(RHS)` (NFC) (#170875)Anatoly Trosinenko2-4/+2
2025-12-09[Hexagon] Use getSigned() for signed valueNikita Popov1-1/+1
2025-12-09[Hexagon] Simplify creation of splat value (NFC)Nikita Popov1-5/+3
2025-12-09[Hexagon] Avoid unnecessary by reference passing (NFC)Nikita Popov1-6/+5
2025-12-09[Hexagon] Remove unnecessarily complicated helpers (NFC)Nikita Popov1-43/+12
2025-12-09[llvm] Use ConstantInt::getAllOnesValue()Nikita Popov1-1/+1
2025-12-08HexagonGenWideningVecInstr.cpp - fix MSVC "result of 32-bit shift implicitly ...Simon Pilgrim1-1/+1
2025-12-04[Hexagon] Fix assignment (#170646)Konrad Kleine1-3/+3
2025-12-04[Hexagon] Fix assert: = -> == (#170643)Konrad Kleine1-1/+1
2025-12-03[Hexagon] Passes for widening vector operations and shuffle opt (#169559)Fateme Hosseini14-25/+2751
2025-12-03[Hexagon] Add an option to use fast FP to int convert for some HVX cases (#16...Fateme Hosseini1-0/+30
2025-12-03[Hexagon][NFC] Drop no-op getMaskedMemoryOpCost/getGatherScatterOpCost stubs ...Shih-Po Hung2-18/+0
2025-12-03[TTI] Use MemIntrinsicCostAttributes for getGatherScatterOpCost (#168650)Shih-Po Hung2-10/+7
2025-12-02[NFC] Refactor TargetLowering::getTgtMemIntrinsic to take CallBase parameter ...Robert Imschweiler2-2/+2
2025-11-26CodeGen: Make all targets override pseudos with pointers (#159881)Matt Arsenault1-0/+2
2025-11-25[NVPTX] Lower LLVM masked vector loads and stores to PTX (#159387)Drew Kersnar2-5/+8
2025-11-19CodeGen: Add subtarget to TargetLoweringBase constructor (#168620)Matt Arsenault1-2/+2
2025-11-19[Hexagon] Enable soft bf16 in hexagon (#167924)Fateme Hosseini7-481/+599
2025-11-19[TTI] Use MemIntrinsicCostAttributes for getMaskedMemoryOpCost (#168029)Shih-Po Hung2-6/+3
2025-11-15[llvm] Delete pointers without null checks (NFC) (#168183)Kazu Hirata1-4/+1
2025-11-15[llvm] Use llvm::copy (NFC) (#168182)Kazu Hirata1-4/+4
2025-11-14MCAsmBackend: Remove unneeded MCAssembler parameterFangrui Song1-7/+7
2025-11-14[RDF] Rename RegisterId field in RegisterRef Reg->Id. NFC (#168154)Craig Topper2-18/+18
2025-11-13[Hexagon] Remove redundant declarations (NFC) (#168014)Kazu Hirata1-5/+0
2025-11-14[Hexagon] Implement isUsedByReturnOnly (#167637)Sudharsan Veeravalli2-0/+40
2025-11-12CodeGen: Remove target hook for terminal rule (#165962)Matt Arsenault1-2/+0
2025-11-12Remove unused standard headers: memory, unordered_* (#167297)serge-sans-paille1-1/+0
2025-11-11[Hexagon] Remove implicit conversions of MCRegister to unsigned. NFC (#167571)Craig Topper3-30/+30
2025-11-11Remove unused <utility> inclusionserge-sans-paille5-5/+0
2025-11-11[Hexagon] Fix a warningKazu Hirata1-1/+1
2025-11-10Hexagon: Enable terminal rule (#165960)Matt Arsenault1-0/+2
2025-11-10CodeGen: Remove TRI arguments from stack load/store hooks (#158240)Matt Arsenault3-15/+12
2025-11-10CodeGen: Remove TRI argument from getRegClass (#158225)Matt Arsenault4-7/+7
2025-11-10CodeGen: Keep reference to TargetRegisterInfo in TargetInstrInfo (#158224)Matt Arsenault4-6/+9
2025-11-10[Hexagon] Implement isMaskAndCmp0FoldingBeneficial (#166891)Sudharsan Veeravalli2-0/+12
2025-11-09[Target] Fix misleading indentation (NFC) (#167206)Kazu Hirata1-1/+1
2025-11-09Remove unused <set> and <map> inclusion (#167175)serge-sans-paille1-1/+0
2025-11-08Remove unused <vector> inclusion (#166997)serge-sans-paille1-1/+0
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